[riscv-port] RFR: 8278994: riscv: RVC support [v2]

[Xiaolin Zheng]

On Fri, 24 Dec 2021 07:13:09 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Xiaolin Zheng has updated the pull request incrementally with three additional commits since the last revision:
>> 
>>  - Cover most RVC instructions by using CompressibleRegion to cover minimal functions in C2
>>  - Revise as proposed comments, including
>>    - Fix macros in assembler_riscv_c.hpp
>>    - Remove UncompressibleRegion
>>    - Modify comments
>>    - Change names: C-Ext to RVC
>>  - Enable RVC instructions (based on the basic patch)
>
> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 1321:
> 
>> 1319: #ifdef ASSERT
>> 1320:     tty->print_cr("pd_patch_instruction_size: instruction 0x%x at " INTPTR_FORMAT " could not be patched!\n", *(unsigned*)branch, p2i(branch));
>> 1321:     Disassembler::decode(branch - 10, branch + 10);
> 
> How is this change tested?

This is a pretty print and I deliberately violated one `movptr` under relocation to test it. If it looks not good I could remove that.

Other comments are fixed in the new patches.

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PR: https://git.openjdk.java.net/riscv-port/pull/34