[riscv-port] RFR: 8279213: riscv: RVB: Add zero/sign extend instructions [v2]

[Feilong Jiang]

On Sat, 25 Dec 2021 03:20:29 GMT, Fei Yang <fyang at openjdk.org> wrote:

> Looks good. Thanks for refactoring the existing zero/sign extension code. Also passed some extra load testing on the unmatched board (where RVB extension is not available).

Thanks for the reviews and tests, Felix. After pushing another commit to add `zext.b`, hotspot and jdk tier1 tests are still passed on QEMU when RVB is enabled.

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PR: https://git.openjdk.java.net/riscv-port/pull/37