[riscv-port] RFR: 8279344: riscv: RVB: Add bitwise rotation instructions [v5]

[Feilong Jiang]

> This PR implements bitwise instructions of RISC-V BitManipulation Extension, including ror/rolw/ror/rori/roriw/rorw.
> 
> This PR also add zext/bext C2 instructions that were missed in JDK-8279213

Feilong Jiang has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR. The pull request contains one new commit since the last revision:

  remove unused imm definition

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Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/39/files
  - new: https://git.openjdk.java.net/riscv-port/pull/39/files/2fd614c1..428e2151

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=04
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=03-04

  Stats: 19 lines in 1 file changed: 19 ins; 0 del; 0 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/39.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/39/head:pull/39

PR: https://git.openjdk.java.net/riscv-port/pull/39