[riscv-port] Integrated: 8276988: riscv: Fix a register name string: lr to x5

[zhengxiaolinX]

On Thu, 11 Nov 2021 09:25:24 GMT, zhengxiaolinX <duke at openjdk.java.net> wrote:

> Hi team -
> 
> Simply fix a register name string: `lr` is `names[1]` so `names[5]` should be `x5`.
> 
> Thanks,
> Xiaolin

This pull request has now been integrated.

Changeset: 30f10b49
Author:    yunyao.zxl <yunyao.zxl at alibaba-inc.com>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.java.net/riscv-port/commit/30f10b4928fc94fd1c57246833673360e88e300b
Stats:     1 line in 1 file changed: 0 ins; 0 del; 1 mod

8276988: riscv: Fix a register name string: lr to x5

Reviewed-by: fyang, shade

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PR: https://git.openjdk.java.net/riscv-port/pull/2