[riscv-port] RFR: 8277968: riscv: Detect vector extension with vcsr [v2]
yadongwang at openjdk.java.net
Tue Nov 30 13:29:29 UTC 2021
On Tue, 30 Nov 2021 08:04:52 GMT, kuaiwei <duke at openjdk.java.net> wrote:
>> UseRVV could cause crash on D1 board(RISCV-C906).
>> It seems that though the D1 board is equipped with RVV-0.7.1 . In our test, VLENB CSR can return value of 16 on D1 board. So JDK will assume it can support RVV extension and crash in vector instructions when UseRVV is enabled.
>> RVV-0.9 and above introduce a new VCSR CSR register, it will raise SIGILL on D1 board. So we can check it to detect vext support.
>>  https://github.com/riscv/riscv-v-spec/blob/0a24d0f61b5cd3f1f9265e8c40ab211daa865ede/v-spec.adoc#vector-extension-programmers-model
>>  https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-extension-programmers-model
> kuaiwei has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR.
> Thanks for your comment. My first thinking is to check /proc/cpuinfo . But it doesn't provide cpu model information. Below is /proc/cpuinfo from Fedora31 on D1:
> [riscv at fedora-riscv ~]$ cat /proc/cpuinfo
> processor : 0
> hart : 0
> isa : rv64imafdcvu
> mmu : sv39
Is it a OS porting problem? See `cat /proc/cpuinfo` from Ubuntu 21.04 on unmatched:
processor : 0
hart : 2
isa : rv64imafdc
mmu : sv39
uarch : sifive,u74-mc
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