Zero support for 32-bit RISC-V

[xiejunfeng (C)]

Thanks Aleksey,

I'll create PR later.

Regards,
Junfeng

----- Original Message-----
To: Aleksey Shipilev [mailto:shade at redhat.com] 
Sent: 2022/4/13 16:38
From: xiejunfeng (C) <xiejunfeng3 at huawei.com>; riscv-port-dev at openjdk.java.net
Subject: Re: Zero support for 32-bit RISC-V

On 4/12/22 11:01, xiejunfeng (C) wrote:
> Hi, I'm adding Zero support for the 32-bit RISC-V architecture.
> 
> I have made an initial patch and it has been successfully cross-compiled:
> 
> $ qemu-riscv32 -L /path/to/riscv32/sysroot 
> /patch/to/riscv-port/openjdk-19-internal/bin/java --version openjdk 
> 19-internal 2022-09-20 OpenJDK Runtime Environment (build 
> 19-internal-adhoc.xiejunfeng.riscv-port)
> OpenJDK Zero VM (build 19-internal-adhoc.xiejunfeng.riscv-port, 
> interpreted mode)
> 
> I am currently testing this.
> 
> You can get the patch here: https://github.com/xiejf2020/riscv-port/commit/20db4468b3738f0daef75ac59c1e7a016556b712 .

That looks fine. I think you can/should PR this to upstream JDK.

The SYS_futex -> SYS_futex_time64 aliasing looks a bit odd, but I think many other projects, including gcc, wasm and others made the similar thing for riscv32.

--
Thanks,
-Aleksey