[riscv-port] RFR: 8282331: riscv: vector register should be saved when RVV is enabled

[Feilong Jiang]

On RISC-V, vector registers should always be saved when RVV is enabled.

Tier1 tests on QEMU with UseRVV enabled are passed without new failures.

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Commit messages:
 - 8282331: riscv: vector register should be saved when RVV is enabled

Changes: https://git.openjdk.java.net/riscv-port/pull/59/files
 Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=59&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8282331
  Stats: 2 lines in 1 file changed: 0 ins; 0 del; 2 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/59.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/59/head:pull/59

PR: https://git.openjdk.java.net/riscv-port/pull/59