[riscv-port] RFR: 8282331: riscv: is_wide_vector should not depend on specific vector size [v3]

[Feilong Jiang]

> On RISC-V, vector registers should always be saved when RVV is enabled.
> 
> Tier1 tests on QEMU with UseRVV enabled are passed without new failures.

Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:

  remove comments

-------------

Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/59/files
  - new: https://git.openjdk.java.net/riscv-port/pull/59/files/7a177a30..9c1bc6cc

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=59&range=02
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=59&range=01-02

  Stats: 1 line in 1 file changed: 0 ins; 1 del; 0 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/59.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/59/head:pull/59

PR: https://git.openjdk.java.net/riscv-port/pull/59