[riscv-port] RFR: 8279344: riscv: RVB: Add bitwise rotation instructions [v7]

[Feilong Jiang]

> This PR implements bitwise instructions of RISC-V BitManipulation Extension, including ror/rolw/ror/rori/roriw/rorw. New C2 instructions are covered by following JTREG tests:
> - test/hotspot/jtreg/compiler/intrinsics/TestRotate.java
> - test/jdk/java/lang 
> 
> This PR also add zext/bext C2 instructions that were missed in JDK-8279213
> 
> Hotspot and jdk tier1 test on QEMU (enable RVB) are passed without new failures.

Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:

  update copyright to 2022

-------------

Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/39/files
  - new: https://git.openjdk.java.net/riscv-port/pull/39/files/92e21821..fe673075

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=06
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=05-06

  Stats: 6 lines in 6 files changed: 1 ins; 0 del; 5 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/39.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/39/head:pull/39

PR: https://git.openjdk.java.net/riscv-port/pull/39