[riscv-port] RFR: 8279344: riscv: RVB: Add bitwise rotation instructions [v9]

[Feilong Jiang]

> This PR implements bitwise instructions of RISC-V BitManipulation Extension, including ror/rolw/ror/rori/roriw/rorw. New C2 instructions are covered by following JTREG tests:
> - test/hotspot/jtreg/compiler/intrinsics/TestRotate.java
> - test/jdk/java/lang 
> 
> This PR also add zext/bext C2 instructions that were missed in JDK-8279213
> 
> Hotspot and jdk tier1 test on QEMU (enable RVB) are passed without new failures.

Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:

  rename some instruct to match its match rule

-------------

Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/39/files
  - new: https://git.openjdk.java.net/riscv-port/pull/39/files/1c519c74..d4e74d53

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=08
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=07-08

  Stats: 41 lines in 2 files changed: 15 ins; 17 del; 9 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/39.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/39/head:pull/39

PR: https://git.openjdk.java.net/riscv-port/pull/39