[riscv-port] RFR: 8279827: riscv: RVB: Add shift and add instructions [v2]
Feilong Jiang
fjiang at openjdk.java.net
Tue Jan 11 12:33:27 UTC 2022
> This PR implements shift left and add instructions: `sh1add`/`sh2add`/`sh3add`/`sh1add.uw`/`sh2add.uw`/`sh3add.uw`.
>
> New C2 instructions are covered by JTREG test: test/jdk/java/lang
Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:
match iRegI instead of iRegIorL2I
-------------
Changes:
- all: https://git.openjdk.java.net/riscv-port/pull/43/files
- new: https://git.openjdk.java.net/riscv-port/pull/43/files/3329fc67..bb1b8580
Webrevs:
- full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=43&range=01
- incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=43&range=00-01
Stats: 6 lines in 1 file changed: 0 ins; 0 del; 6 mod
Patch: https://git.openjdk.java.net/riscv-port/pull/43.diff
Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/43/head:pull/43
PR: https://git.openjdk.java.net/riscv-port/pull/43
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