[riscv-port] Integrated: 8280497: riscv: Undefined Behaviour in class Assembler
Yadong Wang
yadongwang at openjdk.java.net
Thu Jan 27 01:47:04 UTC 2022
On Wed, 26 Jan 2022 05:28:15 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:
> The same problem exists on the riscv platfom. So we follow https://bugs.openjdk.java.net/browse/JDK-8276563.
>
> All instances of type Register exhibit UB in the form of wild pointer (including null pointer) dereferences. This isn't very hard to fix: we should make Registers pointer to something rather than aliases of small integers.
>
> Hotspot/jdk tier1 were passed on the unmatched board. And all jtreg tests have been tested on Qemu without new failures.
This pull request has now been integrated.
Changeset: 65852a6b
Author: Yadong Wang <yadongwang at openjdk.org>
URL: https://git.openjdk.java.net/riscv-port/commit/65852a6b98758604329937bb36ae7a769ef66df2
Stats: 138 lines in 8 files changed: 51 ins; 16 del; 71 mod
8280497: riscv: Undefined Behaviour in class Assembler
Reviewed-by: fyang, fjiang
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PR: https://git.openjdk.java.net/riscv-port/pull/53
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