[riscv-port-jdk17u:riscv-port] Integrated: 8296447: RISC-V: Make the operands order of vrsub_vx/vrsub_vi consistent with RVV 1.0 spec

[Dingli Zhang]

On Wed, 12 Apr 2023 09:06:13 GMT, Dingli Zhang <dzhang at openjdk.org> wrote:

> Please review this backport to riscv-port-jdk17u.
> Backport of [JDK-8296447](https://bugs.openjdk.org/browse/JDK-8296447). 
> A little conflict is that we do not have the `vneg_v` in `macroAssembler_riscv.cpp`
> 
> Tested:
> - jdk/incubator/vector (release/fastdebug with UseRVV on QEMU)
> - tier1 (release with UseRVV on QEMU)

This pull request has now been integrated.

Changeset: 0884e87f
Author:    Dingli Zhang <dzhang at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.org/riscv-port-jdk17u/commit/0884e87f342e0f2d4f1db151230d44c0b9c0e5df
Stats:     20 lines in 2 files changed: 1 ins; 11 del; 8 mod

8296447: RISC-V: Make the operands order of vrsub_vx/vrsub_vi consistent with RVV 1.0 spec

Reviewed-by: fyang, fjiang
Backport-of: 1169dc066c0257da1a237960b8c0cc4782ef8d14

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PR: https://git.openjdk.org/riscv-port-jdk17u/pull/41