[riscv-port-jdk17u:riscv-port] RFR: 8308997: RISC-V: Sign extend when comparing 32-bit value with zero instead of testing the sign bit [v2]

[Gui Cao]

> Hi,
> Please help review this backport to riscv-port-jdk17u.
> Backport of [JDK-8308997](https://bugs.openjdk.org/browse/JDK-8308997). 
> Because there is no [JDK-8294100](https://bugs.openjdk.org/browse/JDK-8294100), [JDK-8301496](https://bugs.openjdk.org/browse/JDK-8301496) here in riscv-port-jdk17u, it will show not clean.
> 
> Testing:
> 
> Tier1-3 passed without new failure on unmacthed (release).

Gui Cao has updated the pull request incrementally with one additional commit since the last revision:

  Use sign_extend instead addw in move32_64

-------------

Changes:
  - all: https://git.openjdk.org/riscv-port-jdk17u/pull/67/files
  - new: https://git.openjdk.org/riscv-port-jdk17u/pull/67/files/aaa63bca..63d429b3

Webrevs:
 - full: https://webrevs.openjdk.org/?repo=riscv-port-jdk17u&pr=67&range=01
 - incr: https://webrevs.openjdk.org/?repo=riscv-port-jdk17u&pr=67&range=00-01

  Stats: 1 line in 1 file changed: 0 ins; 0 del; 1 mod
  Patch: https://git.openjdk.org/riscv-port-jdk17u/pull/67.diff
  Fetch: git fetch https://git.openjdk.org/riscv-port-jdk17u.git pull/67/head:pull/67

PR: https://git.openjdk.org/riscv-port-jdk17u/pull/67