[riscv-port-jdk17u:riscv-port] RFR: 8308997: RISC-V: Sign extend when comparing 32-bit value with zero instead of testing the sign bit [v2]

[Gui Cao]

On Thu, 8 Jun 2023 04:02:41 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Gui Cao has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Use sign_extend instead addw in move32_64
>
> Looks good.

@RealFYang Thanks for the review.

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PR Comment: https://git.openjdk.org/riscv-port-jdk17u/pull/67#issuecomment-1583723051