git: openjdk/riscv-port-jdk17u: riscv-port: 9 new changesets

[duke]

Changeset: ef86ea28
Author:    Matthias Baesken <mbaesken at openjdk.org>
Date:      2023-06-07 07:45:01 +0000
URL:       https://git.openjdk.org/riscv-port-jdk17u/commit/ef86ea2842b1a204834291d9d6665bfcd7b75fbc

8283756: (zipfs) ZipFSOutputStreamTest.testOutputStream should only check inflated bytes

Backport-of: 0c472c8a4ff01b3bc8fba5df82c24c240586e5c5

! test/jdk/jdk/nio/zipfs/ZipFSOutputStreamTest.java

Changeset: b6a5d208
Author:    Matthias Baesken <mbaesken at openjdk.org>
Date:      2023-06-13 07:21:20 +0000
URL:       https://git.openjdk.org/riscv-port-jdk17u/commit/b6a5d2082832c9d70051df8d4a5190f6a6faec58

8269091: javax/sound/sampled/Clip/SetPositionHang.java failed with ArrayIndexOutOfBoundsException: Array index out of range: -4

Backport-of: 1a7b70a8be0a236b98925a8320d25d88a405d595

! src/java.desktop/share/classes/com/sun/media/sound/DirectAudioDevice.java
! test/jdk/javax/sound/sampled/Clip/SetPositionHang.java

Changeset: f80be823
Author:    Oli Gillespie <ogillespie at openjdk.org>
Committer: Aleksey Shipilev <shade at openjdk.org>
Date:      2023-06-13 08:27:53 +0000
URL:       https://git.openjdk.org/riscv-port-jdk17u/commit/f80be8239069ef40cb9b4c0639fba87945a969f0

8304976: Optimize DateTimeFormatterBuilder.ZoneTextPrinterParser.getTree()

Reviewed-by: shade, stsypanov, phh
Backport-of: 438c969b7b07eeef0158b089e5a168849e04bf56

! src/java.base/share/classes/java/time/format/DateTimeFormatterBuilder.java
+ test/micro/org/openjdk/bench/java/time/format/ZonedDateTimeFormatterBenchmark.java

Changeset: e8980486
Author:    Ningsheng Jian <njian at openjdk.org>
Committer: Andrew Haley <aph at openjdk.org>
Date:      2023-06-13 10:10:03 +0000
URL:       https://git.openjdk.org/riscv-port-jdk17u/commit/e8980486da1bbc217cf71251f3d28af5e3e96ecf

8307572: AArch64: Vector registers are clobbered by some macroassemblers

Reviewed-by: aph
Backport-of: 33d9a857308eed53e06b448691910bc8aa2f8fc9

! src/hotspot/cpu/aarch64/aarch64.ad
! src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp
! src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp
! src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp
! src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp
+ test/hotspot/jtreg/compiler/c2/aarch64/TestIntrinsicsRegStress.java

Changeset: 12d08f0c
Author:    Matthias Baesken <mbaesken at openjdk.org>
Date:      2023-06-13 13:12:16 +0000
URL:       https://git.openjdk.org/riscv-port-jdk17u/commit/12d08f0cabefc6b23690b7c3676ffdfb7388a779

8308156: VerifyCACerts.java misses blank in error output

Backport-of: 5a92aae1d967f5be01f05d9cc56c433a5eca61e8

! test/jdk/sun/security/lib/cacerts/VerifyCACerts.java

Changeset: 22a548bc
Author:    Aleksey Shipilev <shade at openjdk.org>
Date:      2023-06-13 17:19:35 +0000
URL:       https://git.openjdk.org/riscv-port-jdk17u/commit/22a548bc3b2ad0b5a9a71a238852ed551d2e1476

8307395: Add missing STS to Shenandoah

Reviewed-by: rkennke
Backport-of: 3968ab5db5443ce93c9a19ebbc5464f7d91782fc

! src/hotspot/share/gc/shenandoah/shenandoahConcurrentGC.cpp

Changeset: 0f531dac
Author:    Christoph Langer <clanger at openjdk.org>
Date:      2023-06-13 13:43:57 +0000
URL:       https://git.openjdk.org/riscv-port-jdk17u/commit/0f531dacb878efe77912688216b0f39a769259a3

8303465: KeyStore of type KeychainStore, provider Apple does not show all trusted certificates

Backport-of: ac41c030030c3d31815474c793ac9c420c47e22c

! src/java.base/macosx/classes/apple/security/KeychainStore.java
! src/java.base/macosx/native/libosxsecurity/KeystoreImpl.m
+ test/jdk/java/security/KeyStore/CheckMacOSKeyChainTrust.java

Changeset: 8ac9c57b
Author:    Goetz Lindenmaier <goetz at openjdk.org>
Date:      2023-06-14 06:38:50 +0000
URL:       https://git.openjdk.org/riscv-port-jdk17u/commit/8ac9c57b75db4d8dbdbd99531fbb0d8b38788587

Merge


Changeset: 131253ae
Author:    Fei Yang <yangfei at iscas.ac.cn>
Date:      2023-06-14 15:35:21 +0000
URL:       https://git.openjdk.org/riscv-port-jdk17u/commit/131253ae92019b323a09070f47f8d5eb461ae799

Merge branch 'master' into riscv-port