git: openjdk/riscv-port-jdk17u: riscv-port: 8296448: RISC-V: Fix temp usages of heapbase register killed by MacroAssembler::en/decode_klass_not_null

[duke]

Changeset: 319154c4
Author:    Dingli Zhang <dingli at iscas.ac.cn>
Committer: GitHub <noreply at github.com>
Date:      2023-03-13 15:02:40 +0000
URL:       https://git.openjdk.org/riscv-port-jdk17u/commit/319154c477e25c16521ab435eec429c76e065df9

8296448: RISC-V: Fix temp usages of heapbase register killed by MacroAssembler::en/decode_klass_not_null


! src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp
! src/hotspot/cpu/riscv/c1_MacroAssembler_riscv.cpp
! src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
! src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
! src/hotspot/cpu/riscv/methodHandles_riscv.cpp
! src/hotspot/cpu/riscv/riscv.ad
! src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp
! src/hotspot/cpu/riscv/stubGenerator_riscv.cpp