Fwd: [openjdk/jdk] 8319716: RISC-V: Add SHA-2 (PR #16562)
Robbin Ehn
rehn at rivosinc.com
Mon Nov 13 13:40:59 UTC 2023
Hey, moving this discussion out of PR.
*>*I think that's what RISC-V profiles are for [1] which make some basic
extensions mandatory. And we already have JVM options like UseRVA20U64 and
UseRVA22U64 for riscv. But there are still some >optional extensions for
each profile, say RVV for RVA22U64. So instead of feeding a rather long
march to the JVM, I feel it's more reasonable to have some JVM options at
the extension level (instead of >sub-extension level) as suggested by
@robehn <https://github.com/robehn>.
>Personally, I would suggest something slightly different. Say:
>"-XX:VectorCryptoExt=all", "-XX:VectorCryptoExt=zvknhb",
"-XX:VectorCryptoExt=zvknhb_zvkb"
>
>This way we will still be able to distinguish specific sub-extensions
while keeping one JVM option for each extension/collection.
>
>[1] https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc
To me it looks like profiles will only work for simple CPUs, UseRVA22U64
only have 23 mandatory extensions and I'm seeing that we may have CPUs with
100+.
And the 'group name' zvkn doesn't work since we are stilling adding new
extensions under it, such as zvknf.
Also we need to consider these may need to be versioned in the future.
I'm conflicted regarding the flags names, on x86 it uses e.g.
UseAVX=<version>.
So UseRVV is more inline with that, UseVectorCrypto is a nicer read, but do
it include zvbb for example ?
In that case UseZvk.. UseZvb.. make more sense.
x86 have a many features without flags e.g. CPU_AVX512_VAES.
It is only turn on if the VM find a CPU supporting this.
I think my suggestion is that we do the same for as many of the extensions
as possible, have no external flag.
Message ID: <openjdk/jdk/pull/16562/review/1726824721 at github.com>
/Robbin
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <https://mail.openjdk.org/pipermail/riscv-port-dev/attachments/20231113/535021d6/attachment.htm>
More information about the riscv-port-dev
mailing list