[riscv-port-jdk11u:riscv-port] Integrated: 8297715: RISC-V: C2: Use single-bit instructions from the Zbs extension

[Gui Cao]

On Wed, 10 Apr 2024 08:00:34 GMT, Gui Cao <gcao at openjdk.org> wrote:

> Hi,
> Please help review this backport to riscv-port-jdk11u.
> Backport of [JDK-8297715](https://bugs.openjdk.org/browse/JDK-8297715).
> The original patch cannot be directly applied because of  we use `experimental(bool, UseZbs, false, "Use Zbs instructions")` in riscv-port-jdk11u instead of OpenJDK higher version`product(bool, UseZbs, false, EXPERIMENTAL, "Use Zbs instructions")`
> 
> The effect is that we could then optimize C2 JIT code for methods like (print with case xml.validation in SPECjvm2008) on qemu system with `-XX:+UnlockExperimentalVMOptions -XX:+UseZbs`:
> Before:
> 
> 03c   	lhu  R28, [R11, #12]	# short, #@loadUS ! Field: com/sun/org/apache/xerces/internal/dom/NodeImpl.flags
> 040 + 	andi  R7, R28, #2	#@andI_reg_imm
> 044 + 	snez  R10, R7	#@convI2Bool
> 048   	# pop frame 32
> 
> 
> After:
> 
> 03c   	lhu  R28, [R11, #12]	# short, #@loadUS ! Field: com/sun/org/apache/xerces/internal/dom/NodeImpl.flags
> 040 + 	bexti  R10, R28, #2	#@convI2Bool_andI_reg_immIpowerOf2
> 044   	# pop frame 32
> 
> 
> ### Testing
> - [x] Run tier1 tests on SOPHON SG2042 (release)

This pull request has now been integrated.

Changeset: f305abc3
Author:    Gui Cao <gcao at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.org/riscv-port-jdk11u/commit/f305abc302bbc66049572d042802e5a48827b817
Stats:     26 lines in 4 files changed: 25 ins; 0 del; 1 mod

8297715: RISC-V: C2: Use single-bit instructions from the Zbs extension

Reviewed-by: fyang, luhenry
Backport-of: d50015af99f44909bf71fd2de97546d47cda86d6

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PR: https://git.openjdk.org/riscv-port-jdk11u/pull/21