CFV: New RISC-V Port Committer: Dingli Zhang

[zifeihan]

Vote: yes

On Thu, Sep 12, 2024 at 3:45 PM zifeihan <decodewar at gmail.com> wrote:

> I hereby nominate Dingli Zhang (dzhang) [0] to RISC-V Port Committer.
>
> He has already made a number of contributions to both trunk [1] and
backporting
> work for RISC-V Port project repos like riscv-port-jdk11u and
riscv-port-jdk17u [2][3].
> Having the committer role would aid this backporting work by avoiding the
need to
> wait for sponsorship of fixes, after review & approval.
> By the way, he currently maintains the jdk RISC-V port on openEuler and
is a maintainer
> of the Java SIG, and expects more backporting in the future.
>
> Votes are due by 9:00 UTC on Thursday 26, September 2024.
>
> Only current RISC-V Port Committer [4] are eligible to vote on this
nomination.
> Votes must be cast in the open replying to this mailing list.
>
> For Lazy Consensus voting instructions, see [5].
>
> Gui Cao
>
> [0] https://openjdk.org/census#dzhang
> [1]
https://github.com/openjdk/jdk/pulls?q=is%3Apr+is%3Aclosed+author%3ADingliZhang
> [2]
https://github.com/openjdk/riscv-port-jdk11u/pulls?q=is%3Apr+is%3Aclosed+author%3ADingliZhang
> [3]
https://github.com/openjdk/riscv-port-jdk17u/pulls?q=is%3Apr+is%3Aclosed+author%3ADingliZhang
> [4] https://openjdk.java.net/census#riscv-port
> [5] https://openjdk.java.net/projects/#committer-vote>

>
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