<div class="__aliyun_email_body_block"><div  style="line-height:1.7;font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;color:#000000;"><div  style="clear:both;">Hi <span >Vladimir,</span></div><div  style="clear:both;"><span ><br ></span></div><div  style="clear:both;"><span >Thank you for the details. But well... I don't have such a FPGA environment. In my view as a <span >substitution maybe JMH could help us reflect this. What I am sure is the compile time would increase with RVC, and I remember it can be reflected in SPECjbb2005's warehouse1; but in my memory I didn't observe a decrease at the final score. <span  style="color:#000000;font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;letter-spacing:normal;text-align:start;text-indent:.0px;text-transform:none;white-space:normal;word-spacing:.0px;background-color:#ffffff;text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline;">I will run JMH and </span><span  style="margin:.0px;padding:.0px;border:.0px;outline:.0px;color:#000000;font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;letter-spacing:normal;text-align:start;text-indent:.0px;text-transform:none;white-space:normal;word-spacing:.0px;background-color:#ffffff;text-decoration-style:initial;text-decoration-color:initial;">Renaissance</span><span  style="color:#000000;font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;letter-spacing:normal;text-align:start;text-indent:.0px;text-transform:none;white-space:normal;word-spacing:.0px;background-color:#ffffff;text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline;"><span > </span>to catch the decrease then.<span > </span></span></span></span></div><div  style="clear:both;"><span ><span ><span  style="color:#000000;font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;letter-spacing:normal;text-align:start;text-indent:.0px;text-transform:none;white-space:normal;word-spacing:.0px;background-color:#ffffff;text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline;"><span ><br ></span></span></span></span></div><div  style="clear:both;"><span ><span ><span  style="color:#000000;font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;letter-spacing:normal;text-align:start;text-indent:.0px;text-transform:none;white-space:normal;word-spacing:.0px;background-color:#ffffff;text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline;"><span >Best,</span></span></span></span></div><div  style="clear:both;"><span ><span ><span  style="color:#000000;font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;letter-spacing:normal;text-align:start;text-indent:.0px;text-transform:none;white-space:normal;word-spacing:.0px;background-color:#ffffff;text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline;"><span >Xiaolin</span></span></span></span></div><div  style="clear:both;"><br /></div><blockquote  style="margin-right:0;margin-top:0;margin-bottom:0;font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;color:#000000;"><div  style="clear:both;">------------------------------------------------------------------</div><div  style="clear:both;">From:Vladimir Kempik <vladimir.kempik@gmail.com></div><div  style="clear:both;">Send Time:2022年9月8日(星期四) 20:24</div><div  style="clear:both;">To:undefined <undefined></div><div  style="clear:both;">Cc:undefined <undefined>; undefined <undefined>; undefined <undefined></div><div  style="clear:both;">Subject:Re: RVC by default?</div><div  style="clear:both;"><br /></div><head ></head>Hello<div  class="">To be more specific, I saw slight perf decrease with RVC only on a core running on fpga.</div><div  class="">On thead c910 results ( -RVC and + RVC) are on par.</div><div  class=""><br  class=""></div><div  class="">Regards, Vladimir<br  class=""><div ><br  class=""><div  class="">8 сент. 2022 г., в 15:09, Xiaolin Zheng <<a  class="" href="mailto:yunyao.zxl@alibaba-inc.com" target="_blank">yunyao.zxl@alibaba-inc.com</a>> написал(а):</div><br  class="Apple-interchange-newline"><div  class=""><div  class="" style="line-height:1.7;font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;"><div  class="" style="clear:both;"><span  class="">Hi Aleksey and Vladimir,</span></div><div  class="" style="clear:both;"><br  class=""></div><div  class="" style="clear:both;">The current RVC support is okay but not complete: it only covers ~10% of total instructions emitted (mostly C2 code, including some part of Stub code), and we might want to transform instructions into the compressed counterparts as much as possible, so maybe the design will change from a whitelist mode (the class CompressibleRegion) to a black list mode. There is one implementation at my local branch <a  class="" href="https://github.com/zhengxiaolinX/jdk/commits/REBASE-rvc-beautify" target="_blank">https://github.com/zhengxiaolinX/jdk/commits/REBASE-rvc-beautify</a> (might not be stable yet, I have not gotten enough time to give it a sufficient test on jtregs and specjbb2015/other benchmarks yet). There are plans reserved to commit them (which cover ~20% of instructions under some tests) after reviewing, but this is currently WIP and waiting loom port to merge first.<br  class=""></div><div  class="" style="clear:both;"><div  class="" style="clear:both;"><br  class=""></div><div  class="" style="clear:both;">And thank you Vladimir for your observations, I will test the Renaissance benchmark as you have mentioned. I have given tests for specjbb2015 months before and found slight performance increase there; as far as I know, the compile time will increase for the transformation logic is extra overhead during the instruction emission phase, such as the code in Assembler::add. Theoretically, when running the compiled code with RVC turning on, though IPC and CPI are not changed, the code size shrinks; I think it should have the same effect as the icache size becoming larger. Maybe something goes wrong? :-) I might need to look into the performance problem in a high priority, so will test the <span  class=" __aliyun_node_has_bgcolor" style="font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;letter-spacing:normal;text-align:start;text-indent:.0px;text-transform:none;white-space:normal;word-spacing:.0px;background-color:#ffffff;float:none;display:inline;">Renaissance</span> first.</div><div  class="" style="clear:both;"><br  class=""></div><div  class="" style="clear:both;">Best,</div><span  class="">Xiaolin</span></div><div  class="" style="clear:both;"><br  class=""></div><div  class="" style="clear:both;">------------------------------------------------------------------</div><div  class="" style="clear:both;">From:Aleksey Shipilev <<a  class="" href="mailto:shade@redhat.com" target="_blank">shade@redhat.com</a>></div><div  class="" style="clear:both;">Send Time:2022年9月8日(星期四) 18:34</div><div  class="" style="clear:both;">To:undefined <undefined>; undefined <undefined></div><div  class="" style="clear:both;">Subject:RVC by default?</div><div  class="" style="clear:both;"><br  class=""></div>Hi,<br  class=""><br  class="">I was looking at some generated code on RISC-V, and realized while we have RVC support, we don't <br  class="">enable it by default. On HiFive Unleashed:<br  class=""><br  class="">$ test-jdk/bin/java -XX:+UnlockExperimentalVMOptions -XX:+PrintFlagsFinal 2>&1 | grep RVC<br  class="">      bool UseRVC                                   = false                           {ARCH <br  class="">experimental} {default}<br  class=""><br  class=""><br  class="">Is there a reason not to do RVC by default? Can we reliably poll the RVC capabilities in current <br  class="">hardware?<br  class=""><br  class="">-- <br  class="">Thanks,<br  class="">-Aleksey</div></div></div><br  class=""></div></blockquote></div></div>