<div class="__aliyun_email_body_block"><div style="line-height:1.7;font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;color:#000000;"><div style="clear:both;"><span >Hi Felix,</span></div><div style="clear:both;"><br ><div style="clear:both;">Thank you for the reasonable advice and the time taken for the pre-reviews. I consider this a very nice approach to removing some complexities for MachBranchNodes in the first patches. We can certainly put them afterward to investigate the effectiveness of compressing MachBranchNode things. So will do that.</div><div style="clear:both;"><br ></div><div style="clear:both;">Thanks,</div><span >Xiaolin</span></div><div style="clear:both;"><br /></div><blockquote style="margin-right:0;margin-top:0;margin-bottom:0;font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;color:#000000;"><div style="clear:both;">------------------------------------------------------------------</div><div style="clear:both;">From:yangfei <yangfei@iscas.ac.cn></div><div style="clear:both;">Send Time:2022年9月24日(星期六) 16:06</div><div style="clear:both;">To:郑孝林(云矅) <yunyao.zxl@alibaba-inc.com></div><div style="clear:both;">Cc:riscv-port-dev <riscv-port-dev@openjdk.org></div><div style="clear:both;">Subject:Re: Re: Re: Discuss the RVC implementation</div><div style="clear:both;"><br /></div><br >
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Hi Xiaolin,
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Thanks for the explaination.
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From your codesize metrics, I see a very low possibility of compressing those branch instructions (beq/bne).
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So it looks to me that another way to consider here would be not compress these sort of instructions at all.
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Then the case will be simplified and we won't lose much here.
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Thanks,
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Fei
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-----Original Messages-----<br >
<b >From:</b><span id="rc_from">"Xiaolin Zheng" <yunyao.zxl@alibaba-inc.com></span><br >
<b >Sent Time:</b><span id="rc_senttime">2022-09-23 21:11:57 (Friday)</span><br >
<b >To:</b> yangfei <yangfei@iscas.ac.cn><br >
<b >Cc:</b> riscv-port-dev <riscv-port-dev@openjdk.org><br >
<b >Subject:</b> Re: Re: Discuss the RVC implementation<br >
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<span >I forgot to describe something about MachBranchNodes.</span>
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The thing is, C2 needs to calculate node sizes to allocate buffers, so it has a scratch_emit phase to estimate node size first. It uses a clever strategy to measure MachBranchNodes' size. When estimating the size, we could find only the MacnBranchNode itself matters, not the Label. The labels are just tools for generating branch instructions. So there has "fake label"[1] instead, directly placed at the same pc as the MachBranchNode's to simplify code logic.
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On other platforms like x86 and aarch64, the size of branch instructions is not changed, and these platforms don't have a code size reduction extension as RISC-V. For example, on other platforms, the jcc is jcc, and the bl is bl. In our implementation, we have:
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```
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#define INSN(NAME) \
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void NAME(Register Rd, const int32_t offset) { \
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/* jal -> c.j */ \
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if (do_compress() ...) { \
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c_j(offset); \
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return; \
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} \
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_jal(Rd, offset); \
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}
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INSN(jal);
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#undef INSN
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```
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The size of an emitted instruction is determined by the `offset`. Though reasonable, it is not compatible with the "fake label" strategy. For example, with the "fake label", the offset is always 0 when scratch-emitting a MachBranchNode. The offset does not match the real offset. Therefore, In scratch_emit and the real emission, the size of MachBranchNode might be different, which will break the assumption of C2's strategy.
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To emit the code that we want, a basic approach is to pass the real offset into the MachBranchNode, and let us read it instead of the "0" every time.
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So currently in these patches, all MachBranchNodes are temporarily incompressible in C2 when RVC is enabled.
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