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<span style="font-size:14px;font-family:Arial;">Hi,</span>
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<span style="font-size:14px;font-family:Arial;"><br>
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<span style="font-family:Arial;">Making </span><span style="font-family:Arial;font-size:14px;white-space:normal;"><span style="font-family:Arial;">RVA20U64 profile the default makes sense to me provided that works for current accessible</span><span style="font-family:Arial;"> mainstream RV hardwares</span><span style="font-family:Arial;">.</span></span>
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<span style="font-size:14px;font-family:Arial;">Please note that </span><span style="font-family:Tahoma, Arial, STHeiti, SimSun;font-size:14px;white-space:normal;"><span style="font-size:14px;font-family:Arial;">RVA20U64 profile</span><span style="font-size:14px;font-family:Arial;"> also means availability of the </span><span style="font-size:14px;font-family:Arial;">Zicclsm extention which indicates support for </span><span style="font-size:14px;font-family:Arial;">unaligned loads/stores [1]</span><span style="font-size:14px;font-family:Arial;">.</span><span style="font-size:14px;font-family:Arial;"></span></span>
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<span style="font-size:14px;font-family:Arial;"> "</span><span style="background-color:#FFFFFF;color:#24292F;font-family:Arial;font-size:14px;box-sizing:border-box;font-weight:600;">Zicclsm</span><span style="background-color:#FFFFFF;color:#24292F;font-family:Arial;font-size:14px;"> Misaligned loads and stores to main memory regions with both the cacheability and coherence PMAs must be supported."</span>
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<span style="font-family:Arial;">Thanks,</span>
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<span style="font-family:Arial;">Fei</span>
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<span style="font-size:14px;font-family:Arial;">[1] </span><span style="font-family:Arial;font-size:14px;">https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva20-profiles</span>
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-----Original Messages-----<br>
<b>From:</b><span id="rc_from">"Xiaolin Zheng" <yunyao.zxl@alibaba-inc.com></span><br>
<b>Sent Time:</b><span id="rc_senttime">2022-11-07 17:43:28 (Monday)</span><br>
<b>To:</b> "Vladimir Kempik" <vladimir.kempik@gmail.com><br>
<b>Cc:</b> riscv-port-dev <riscv-port-dev@openjdk.org><br>
<b>Subject:</b> Re: RVC by default (cont'd)<br>
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Hi Vladimir,
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Thank you for the suggestion and that sounds nice as well to me - more unified.
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Pushed a new commit to fit your pre-review comment.
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Best,
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Xiaolin
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[1] <span><a href="https://github.com/zhengxiaolinX/jdk/commit/312462e83ea3dcbd884e121ca16b2209b7a6c5c4" target="_blank">https://github.com/zhengxiaolinX/jdk/commit/312462e83ea3dcbd884e121ca16b2209b7a6c5c4</a></span>
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From:Vladimir Kempik <vladimir.kempik@gmail.com>
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Send Time:2022年11月7日(星期一) 17:05
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To:郑孝林(云矅) <yunyao.zxl@alibaba-inc.com>
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Cc:riscv-port-dev <riscv-port-dev@openjdk.org>
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Subject:Re: RVC by default (cont'd)
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Hello<br>
Recently commit [1] introduced support for cpu profiles, for example RVA20U64, RVA22U64.<br>
And UseRVC is already a part of UseRVA20U64.<br>
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Maybe it would be good to go another way. For example make RVA20U64 non experimental and enable it by default, that will enable RVC automatically. Also make UseRVC non-experimental.<br>
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Regards, Vladimir<br>
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[1] https://github.com/openjdk/jdk/commit/e0c29307f7b35149aacae0bb935aa9fe524cff72<br>
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> 7 нояб. 2022 г., в 07:17, Xiaolin Zheng <yunyao.zxl@alibaba-inc.com> написал(а):<br>
> <br>
> Hi team,<br>
> <br>
> As RVC's proposed patches have been merged into the mainline, in response to the former thread[1] I would like to turn it on by default before the December RDP 1 deadline, for currently the hardware feature C extension has been ratified and implemented by mainstream RISC-V hardware like boards produced by Hifive, meaning we can test and verify our implementation on physical boards.<br>
> <br>
> Opening another thread to refresh the content.<br>
> <br>
> We can turn RVC on for now by using `-XX:+UnlockExperimentalVMOptions -XX:+UseRVC`. In addition we can examine the generated code by using options `-XX:+UnlockExperimentalVMOptions -XX:+UseRVC -XX:+UnlockDiagnosticVMOptions -XX:+PrintAssembly -XX:PrintAssemblyOptions=no-aliases,numeric,show-bytes` combined.<br>
> <br>
> I have pushed a simple proposed patch[2] to turn it as default true.<br>
> <br>
> The only thing I shall mention here is as we know there is a known issue that may relate to the opensbi lib. Please see previous discussions[3][4]. The pattern of that issue is very easy to be distinguished, which is an uncommon case and which turns out to be bugs hidden in underlying libraries at last. I think it should be users' responsibility to update their outdated libs, and such issue shall not stop our pace.<br>
> <br>
> I have opened an JBS issue[5] to record this, marking it as "Won't fix".<br>
> <br>
> If there's any suggestion or objection, please let me know. If not, I will file a patch around Nov 15 (may be next week since the deadline is looming) if everything looks okay.<br>
> <br>
> Best Regards,<br>
> Xiaolin<br>
> <br>
> [1] https://mail.openjdk.org/pipermail/riscv-port-dev/2022-September/000609.html<br>
> [2] https://github.com/zhengxiaolinX/jdk/commit/b5b9c64529c27c40542f8cda720652fabf70682d<br>
> [3] https://mail.openjdk.org/pipermail/riscv-port-dev/2022-September/000618.html<br>
> [4] https://github.com/riscv-collab/riscv-openjdk/issues/23<br>
> [5] https://bugs.openjdk.org/browse/JDK-8296350<br>
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