<div class="__aliyun_email_body_block"><div  style="line-height:1.7;font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;color:#000000;"><div  style="clear:both;">Hi team,<br ></div><div  style="clear:both;"><br ></div><div  style="clear:both;">We would like to discuss the RISC-V OpenJDK11u port.</div><div  style="clear:both;"><br ></div><div  style="clear:both;"><span >Currently seems no one claims this port yet, and it would be a pleasure for us if we (from Alibaba) could take the backporting work.</span></div><div  style="clear:both;"><span ><br ></span></div><div  style="clear:both;"><span >We have a backport [1] [2] on Alibaba Dragonwell11 (downstream of our OpenJDK11) that works fine currently, though backported from the initial load of the riscv-port repo [3] at the beginning of the last year. We are currently thinking of contributing that to the upstream, despite that various polishing, patch splitting, and further backporting to meet the requirements of backports are needed. So <span  style="color:#000000;font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;letter-spacing:normal;text-align:start;text-indent:.0px;text-transform:none;white-space:normal;word-spacing:.0px;background-color:#ffffff;text-decoration-thickness:initial;text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline;">obviously </span>it is not a "ready-to-go" one like the 17u port [4] by Yadong.</span></div><div  style="clear:both;"><span ><br ></span></div><div  style="clear:both;"><span >Some challenging parts might be the differences between the gaps in 11u and 19 and above. For example, on 11u we do not have a VecA implementation, yet, the RVV vector extension in the RISC-V backend [5] in the mainline needs it. The VecA implementation may look currently unlikely to get permission to backport since the changes [6] in shared code. Without VecA, C2 vector intrinsics and the VectorAPI-related code may not work, but intrinsics using vector registers directly could work as expected, like `<span >StubGenerator::<span >copy_memory_v`.</span></span></span></div><div  style="clear:both;"><span ><span ><span ><br ></span></span></span></div><div  style="clear:both;"><span ><span ><span >Looking forward to further discussions.</span></span></span></div><div  style="clear:both;"><span ><span ><span ><br ></span></span></span></div><div  style="clear:both;"><span ><span ><span >Best Regards,</span></span></span></div><div  style="clear:both;"><span ><span ><span >Xiaolin</span></span></span></div><div  style="clear:both;"><span ><br ></span></div><div  style="clear:both;"><span >[1] <span ><a  href="https://github.com/alibaba/dragonwell11/commit/959fa35e24714f63c9e8d835268e3a9aef898a22" target="_blank">https://github.com/alibaba/dragonwell11/commit/959fa35e24714f63c9e8d835268e3a9aef898a22</a></span></span></div><div  style="clear:both;"><span >[2] <span ><a  href="https://github.com/alibaba/dragonwell11/issues/209" target="_blank">https://github.com/alibaba/dragonwell11/issues/209</a></span></span></div><div  style="clear:both;"><span >[3] <span ><a  href="https://github.com/openjdk/riscv-port/pull/1" target="_blank">https://github.com/openjdk/riscv-port/pull/1</a></span></span></div><div  style="clear:both;"><span >[4] <span ><a  href="https://github.com/openjdk/riscv-port-jdk17u/pull/1" target="_blank">https://github.com/openjdk/riscv-port-jdk17u/pull/1</a></span></span></div><div  style="clear:both;"><span >[5] <span ><a  href="https://github.com/openjdk/jdk/blob/master/src/hotspot/cpu/riscv/riscv.ad#L240-L243" target="_blank">https://github.com/openjdk/jdk/blob/master/src/hotspot/cpu/riscv/riscv.ad#L240-L243</a></span></span></div><div  style="clear:both;"><span >[6] <span ><a  href="https://bugs.openjdk.org/browse/JDK-8231441" target="_blank">https://bugs.openjdk.org/browse/JDK-8231441</a></span></span></div></div></div>