RFR: 8365732: RISC-V: implement AES CTR intrinsics [v7]

[Anjian Wen]

On Fri, 19 Sep 2025 07:09:27 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Anjian Wen has updated the pull request with a new target base due to a merge or a rebase. The incremental webrev excludes the unrelated changes brought in by the merge/rebase. The pull request contains eight additional commits since the last revision:
>> 
>>  - Merge branch 'openjdk:master' into aes_ctr
>>  - fix the counter increase at limit and add test
>>  - change format
>>  - update reg use and instruction
>>  - change some name and format
>>  - delete useless Label, change L_judge_used to L_slow_loop
>>  - add Flags and fix the stubid name
>>  - RISC-V: implement AES-CTR mode intrinsics
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 2667:
> 
>> 2665:     __ addi(t0, counter, 8);
>> 2666:     __ ld(tmp, Address(t0));
>> 2667:     __ rev8(tmp, tmp);
> 
> Note that `rev8` is only available under `UseZbb`. Maybe you should use `revb/revbw` instead which considers that the availability of Zbb extension.

I used the zbb and zvbb instructions in my patch，which seem not easy to replace in vector operations, and there are some optimizations when using them, so I think we may add a extension check in vm_version_riscv.cpp?

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PR Review Comment: https://git.openjdk.org/jdk/pull/25281#discussion_r2365883933