RFR: Some more AArch64 CAS/CAE fixes

[Roman Kennke]

Am Freitag, den 18.11.2016, 14:41 +0100 schrieb Aleksey Shipilev:
> On 11/17/2016 09:11 PM, Roman Kennke wrote:
> > 
> > http://cr.openjdk.java.net/~rkennke/aarch64-cas/webrev.02/
> 
> *) I don't quite get the NoSp change. The change now allows some
> operands to take SP. Was it an overlook, or AArch64 really has some
> constraints about this?

Input (read-only) registers can be anything. It is important that
output (write-to) registers are *not* SP (e.g. the current thread or
heap-base registers). We had a few places where the result or tmp
registers was including SP, e.g. :

-instruct compareAndSwapNAcq_shenandoah(iRegINoSp res, indirect mem,
iRegNNoSp oldval, iRegNNoSp newval, iRegP tmp, rFlagsReg cr) %{
+instruct compareAndSwapNAcq_shenandoah(iRegINoSp res, indirect mem,
iRegN oldval, iRegN newval, iRegNNoSp tmp, rFlagsReg cr) %{



> *) src/cpu/aarch64/vm/macroAssembler_aarch64.cpp:
> 
> Missed one:
>    if (size == word) {
> 
> Would appreciate parentheses here:
>    bool is_cae = result != noreg;
>    bool is_narrow = size == word;

Fixed:

http://cr.openjdk.java.net/~rkennke/aarch64-cas/webrev.03/

ok?

Roman