RFR: 8293007: riscv: optimize nmethod entry barrier

[Yadong Wang]

On Mon, 29 Aug 2022 11:15:30 GMT, Aleksey Shipilev <shade at openjdk.org> wrote:

>> https://bugs.openjdk.org/browse/JDK-8290700 introduced a faster nmethod entry barrier: a out-of-line stub to the entry barriers of C2 methods, and also a concurrent-data-and instruction-patching barrier.
>> Porting loom and generational ZGC are both under development in progress in riscv port project, and we brought the similar modification to make things smooth. 
>> 
>> Tier1 passed on unmatched, and also full jtreg tests tested on qemu user mode without new failures.
>
> src/hotspot/cpu/riscv/gc/shared/barrierSetAssembler_riscv.cpp line 192:
> 
>> 190: 
>> 191: void BarrierSetAssembler::clear_patching_epoch() {
>> 192:   _patching_epoch = 0;
> 
> Don't we want `Atomic::store(&_patching_epoch, 0)` here?

We can do a relax clear here, because clear_patching_epoch() was only called by arm_all_nmethods(), which happened always in the safepoint.

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PR: https://git.openjdk.org/jdk/pull/10056