RFR: 8283186: Explicitly pass a third temp register to MacroAssembler::store_heap_oop

[Thomas Schatzl]

Hi all,

  can I have reviews for this change that explicitly passes a third temp parameter to `MacroAssembler::store_heap_oop` so that `G1BarrierSetAssembler::oop_store_at` (and the equivalent Shenandoah code) does not need to invent some out of thin air? This makes the code much less surprising.

The interesting part of this change is probably the first hunk in `src/hotspot/cpu/x86/templateTable_x86.cpp`, the rest is just passing on that additional parameter.

Testing: gha

Thanks,
  Thomas

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Commit messages:
 - initial version

Changes: https://git.openjdk.java.net/jdk/pull/7820/files
 Webrev: https://webrevs.openjdk.java.net/?repo=jdk&pr=7820&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8283186
  Stats: 58 lines in 16 files changed: 2 ins; 2 del; 54 mod
  Patch: https://git.openjdk.java.net/jdk/pull/7820.diff
  Fetch: git fetch https://git.openjdk.java.net/jdk pull/7820/head:pull/7820

PR: https://git.openjdk.java.net/jdk/pull/7820