RFR: 8293769: RISC-V: Add a second temporary register for BarrierSetAssembler::load_at

[Fei Yang]

On Wed, 14 Sep 2022 08:03:12 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/gc/shenandoah/shenandoahBarrierSetAssembler_riscv.cpp line 318:
>> 
>>> 316:     __ push_call_clobbered_registers();
>>> 317: 
>>> 318:     satb_write_barrier_pre(masm, noreg, dst, xthread, tmp, t0, true, false);
>> 
>> Is `tmp` not `t0` here? I expected to see `t1` in this diff. Maybe I am missing something.
>
> I don't think 'tmp' is 't0' here since we are asserting they are different registers in ShenandoahBarrierSetAssembler::satb_write_barrier_pre [1]. And I also run non-trivial benchmark work loads like Dacapo, Specjvm and Specjbb using ShenandoahGC with fastdebug build for these changes. 
> 
> [1] https://github.com/openjdk/jdk/blob/master/src/hotspot/cpu/riscv/gc/shenandoah/shenandoahBarrierSetAssembler_riscv.cpp#L111

PS: Also eyeballed all possible callers of ShenandoahBarrierSetAssembler::satb_write_barrier_pre and I think we are safe here :-)

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PR: https://git.openjdk.org/jdk/pull/10261