RFR: 8370947: Mitigate Neoverse-N1 erratum 1542419 negative impact on GCs and JIT performance [v28]

[Evgeny Astigeevich]

On Thu, 19 Feb 2026 16:31:43 GMT, Aleksey Shipilev <shade at openjdk.org> wrote:

> Took a brief look, and I already have questions. Feels like we need to look at simplifications.
> 
> Overall, I do not completely understand the dependencies between `UseDeferredICacheInvalidation`, `NeoverseN1...`, DIC/IDC features. Is there a way to simplify this? For example, always opt into deferred invalidation, and then let deferred invalidation code mitigate the errata?

Let me try to explain.
`UseDeferredICacheInvalidation` means to do single icache invalidation instead of multiple invalidations. Maybe we should rename it to `UseSingleICacheInvalidation`? This cannot be enabled by default because hardware needs to support this feature.

AArch64 can do a single invalidation if full hardware cache coherence is enable. DIC/IDC bits of [CTR_EL0](https://developer.arm.com/documentation/ddi0601/2025-12/AArch64-Registers/CTR-EL0--Cache-Type-Register?lang=en) indicate what hardware cache coherence is available. So we check those bits and enable `UseDeferredICacheInvalidation` if they are set.

>  I.e. if you don't defer, you get no mitigation, you eat the cost of `__builtin_clear_cache` all the time.

`NeoverseN1Errata1542419` is mostly a diagnostic flag which shows whether N1 is affected. An affected N1 has DIC bit disabled. This means `UseDeferredICacheInvalidation` won't be enabled. So no deferred invalidation. However we need deferred single invalidation.

We automatically, if an user does not use cmd options, detect whether we can use single invalidation and need mitigation of the errata.

I'll update the description of the PR and comments of the code.

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PR Comment: https://git.openjdk.org/jdk/pull/28328#issuecomment-3930454177