[lworld+fp16] RFR: 8308363: Initial compiler support for FP16 scalar operations.

[Jatin Bhateja]

On Mon, 22 May 2023 17:07:42 GMT, Jatin Bhateja <jbhateja at openjdk.org> wrote:

> Starting with 4th Generation Xeon, Intel has made extensive extensions to existing ISA to support 16 bit scalar and vector floating point operations based on IEEE 754 FP16 format.
> 
> We plan to support this in multiple stages spanning across Java side definition of Float16 type, scalar operation and finally SLP vectorization support.
> 
> This patch adds  minimal Java and Compiler side support for one API Float16.add.
> 
> Following is the gist of changes introduced with the patch :-
> 
> - Minimal implementation of Float16 primitive class supporting one operation (Float16.add)
> - X86 AVX512-FP16 feature detection at VM startup.
> - C2 IR and Inline expander changes for Float16.add API.
> - FP16 constant folding handling.
> - Backend support : Instruction selection patterns and assembler support.
> 
> Please review and share your feedback.
> 
> Best Regards,
> Jatin

> ### Webrevs
> * 00: [Full](https://webrevs.openjdk.org/?repo=valhalla&pr=848&range=00) ([98d8ea1f](https://git.openjdk.org/valhalla/pull/848/files/98d8ea1f207eca16d1f8bf02f55115ecbea16f15))

![image](https://github.com/openjdk/valhalla/assets/59989778/fa9438b5-f893-4a61-a5da-4eed6de32a27)

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PR Comment: https://git.openjdk.org/valhalla/pull/848#issuecomment-1572262949