[lworld+fp16] RFR: 8338102: x86 backend support for newly added Float16 intrinsics.

[Jatin Bhateja]

On Fri, 9 Aug 2024 10:35:31 GMT, Jatin Bhateja <jbhateja at openjdk.org> wrote:

> This patch enables newly added Float16 intrinsicfication support added by [JDK-8336406](https://bugs.openjdk.org/browse/JDK-8336406) for x86 targets supporting AVX512_FP16 feature.
> 
> Kindly review and approve.
> 
> Best Regards,
> Jatin
> 
> Hi @Bhavana-Kilambi, 
> On a second thought, do you see a possibility of sharing the IR nodes by appending secondary opcode to shared IR node in applicable scenarios, so we can have one IR for each class of operations (unary / binary / secondary).  It may need defining following new matcher routines and some more interfaces:- 
> 
>    match_rule_supported_shared(int primary_opcode, int secondary_opcode)
>    match_rule_supported_vector_shared (int primary_opcode, int secondary_opcode, int vlen, BasicType bt)
>    VectorNode::opcode(int popc, int sopc, BasicType bt)
> 
> BinaryOpNode (Dst, Src1, Src2, immI_Opcode);   
> 
> 
> Secondary opcode being a immediate operand can be accessed by encoding routines. WDYT ?
> 
> Another possibility could be to encode both primary and secondary opcodes in existing opcode without disturbing the interfaces and add relevant helper routines to extract primary / secondary opcodes, I think opcodes are never -ve values, hence secondary opcode could be accommodated into higher order bits starting from (MSB-1).

FTR, other missing intrinsics are conversion operations (Float16.longValue/intValue/doubleValue etc), x86 FP16 ISA has direct instructions for conversions from / to Float16 values..

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PR Comment: https://git.openjdk.org/valhalla/pull/1196#issuecomment-2277691737