[lworld+fp16] RFR: 8338061: Add support for FP16 unary and ternary operations

[Bhavana Kilambi]

On Tue, 20 Aug 2024 09:38:38 GMT, Bhavana Kilambi <bkilambi at openjdk.org> wrote:

>> src/hotspot/share/opto/compile.cpp line 3691:
>> 
>>> 3689:   case Op_SqrtHF:
>>> 3690:   case Op_FmaHF:
>>> 3691:   // Count all float operations that may use FPU
>> 
>> Hey @Bhavana-Kilambi , I am little worried about introducing specialized IR nodes as discussed in [pervious thread](https://github.com/openjdk/valhalla/pull/1196#issuecomment-2283627677),  even though our current strategy fits well with C2 compilation flow without causing much disturbance, going forward we may need to support other reduced precision types BF16 (AVX10.2 has several ISA extensions for BF16), FP8 and INT8, creating unique IR may not be desirable, lets revisit this after features completion with conversion ops.
>
> Yes,  I do agree we would have an explosion of IR nodes if we have to add support for INT8, FP8, Bfloat16 etc..
> For now, I guess I will just create specialized IR until we have decided on how to get them integrated into a single IR using a secondary imm opcode (or if others in the community have any other idea).

I have the conversion ops and isFinite/Infinite/NaN intrinsics still left to complete.

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PR Review Comment: https://git.openjdk.org/valhalla/pull/1211#discussion_r1723076212