[lworld+fp16] RFR: 8330021: AArch64: Add backend support for FP16 add operation [v4]

[Jatin Bhateja]

On Fri, 5 Jul 2024 10:59:44 GMT, Bhavana Kilambi <bkilambi at openjdk.org> wrote:

>> test/hotspot/jtreg/compiler/intrinsics/float16/TestFP16ScalarAdd.java line 58:
>> 
>>> 56:     @Test
>>> 57:     @IR(applyIfCPUFeature = {"avx512_fp16", "true"}, counts = {IRNode.ADD_HF, "> 0", IRNode.REINTERPRET_S2HF, "> 0", IRNode.REINTERPRET_HF2S, "> 0"})
>>> 58:     @IR(applyIfCPUFeatureAnd = {"fphp", "true", "asimdhp", "true"}, counts = {IRNode.ADD_HF, "> 0", IRNode.REINTERPRET_S2HF, "> 0", IRNode.REINTERPRET_HF2S, "> 0"})
>> 
>> Please have one IR rules with unified feature list for x86 and aarach64. 
>> Not sure, but asimdhp is only needed for SIMD instructions I guess.
>
> Thanks @jatin-bhateja for your comments.
> On Neon (non-SVE) machines or when we are testing scalar FP16 operations, Float16 is supported only if both `fphp` and `asimdhp` features are supported. So if we have to write it as a single rule, it needs to be something like - `avx512_fp16 == true || (fphp == true && asimdhp == true)` and I wasn't sure if this can be done in single IR rule here. Where ever I could write it as a single rule, I have done that for ex. clubbing `avx512_fp16` and `sve` in the same IR rule for `TestFloat16VectorSum.java`.

I see, only way i can think of circumventing it currently is by creating a different test for AARCH64 as done for [some other tests](https://github.com/openjdk/jdk/tree/master/test/hotspot/jtreg/compiler/vectorapi/reshape)
 * @requires vm.cpu.features ~= ".*avx512bw.*"
 * @requires vm.cpu.features ~= ".*sve.*"

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PR Review Comment: https://git.openjdk.org/valhalla/pull/1096#discussion_r1666736666