[lworld+fp16] RFR: 8330021: AArch64: Add backend support for FP16 add operation

[Bhavana Kilambi]

On Mon, 6 May 2024 18:28:31 GMT, Bhavana Kilambi <bkilambi at openjdk.org> wrote:

> This commit [1] adds initial support for FP16 operations and adds backend support for FP16 add operation for X86. This task adds backend support for scalar and vector FP16 add operation on aarch64.
> 
> [1] https://github.com/openjdk/valhalla/commit/f03fb4e4ee4d59ed692d0c26ddce260511f544e7#diff-a799ce8da7f3062bb3699beb65aae504840c649942032e325c2a50f88a2869ad

test/hotspot/gtest/aarch64/aarch64-asmtest.py line 19:

> 17:         0x7e0, 0xfc0, 0x1f80, 0x3ff0, 0x7e00, 0x7e00,
> 18:         0x8000, 0x81ff, 0xc1ff, 0xc003, 0xc7ff, 0xdfff,
> 19:         0xe03f, 0xe1ff, 0xf801, 0xfc00, 0xfc07, 0xff03,

Removed "0xe10f" from the list as it is not a valid 16-imemdiate. 
Source : https://gist.github.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a

test/hotspot/jtreg/compiler/intrinsics/float16/TestFP16ScalarAdd.java line 99:

> 97:     @IR(applyIfCPUFeature = {"avx512_fp16" , "true"}, counts = {IRNode.CONVF2HFANDS2HF, " >= 1"})
> 98:     @IR(applyIfCPUFeatureAnd = {"fphp", "true", "asimdhp", "true"}, counts = {IRNode.CONVF2HFANDS2HF, " >= 1"})
> 99:     public void test3() {

"test3" and "test4" are not exactly related to FP16 add operation and I can move them to another file if needed.

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PR Review Comment: https://git.openjdk.org/valhalla/pull/1096#discussion_r1592194879
PR Review Comment: https://git.openjdk.org/valhalla/pull/1096#discussion_r1592188182