[lworld] RFR: 8376059: [lworld] Fix the issues in code generation of StoreLSpecialNode [v2]

[Quan Anh Mai]

On Tue, 3 Feb 2026 09:22:33 GMT, Tobias Hartmann <thartmann at openjdk.org> wrote:

>> Quan Anh Mai has updated the pull request incrementally with two additional commits since the last revision:
>> 
>>  - Saving the register in the slow path instead
>>  - recompute tmp4 instead of saving it
>
> src/hotspot/cpu/aarch64/gc/g1/g1_aarch64.ad line 79:
> 
>> 77: // - Do no set/overwrite barrier data here, also handle G1C2BarrierPostNotNull
>> 78: // - Move this into the .m4?
>> 79: instruct g1StoreLSpecialOneOopOff0(indirect mem, iRegLNoSp src, immI0 off, iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, rFlagsReg cr)
> 
> Should we do the same on x64?

Yes you are right, I have fixed these issues on x64, too.

> src/hotspot/cpu/aarch64/gc/g1/g1_aarch64.ad line 119:
> 
>> 117: 
>> 118:     // Adjust address to point to narrow oop
>> 119:     __ add($tmp4$$Register, $mem$$Register, 4);
> 
> I think we should have asserts on `oop_off_1` and `oop_off_2` in `StoreFlatNode::expand_atomic` that check that `off` is either zero or four. Otherwise we would hit a "bad ad file" failure during matching. Also, a comment explaining that this is due to alignment constraints would be nice.

Done

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PR Review Comment: https://git.openjdk.org/valhalla/pull/2013#discussion_r2758983892
PR Review Comment: https://git.openjdk.org/valhalla/pull/2013#discussion_r2758985511