RFR: 8199138: Add RISC-V support to Zero

[Andrew Haley]

On 03/18/2018 08:19 PM, Edward Nevill wrote:
> Pretty much. The only atomic operation which doesn't used GCC builtins is os::atomic_copy64. For RISC-V this just does the same as all other 64 bit CPUs.
> 
>     *(jlong *) dst = *(const jlong *) src;

That's probably wrong, but it'll do for now.  We'll need something better
in the future.  GCC's __atomic_{load,store} (__ATOMIC_RELAXED) would do it.

-- 
Andrew Haley
Java Platform Lead Engineer
Red Hat UK Ltd. <https://www.redhat.com>
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