RFR: 8199138: Add RISC-V support to Zero

[John Paul Adrian Glaubitz]

On 03/27/2018 05:23 PM, Edward Nevill wrote:
> Sorry for the delay. I was doing another test build on qemu which takes about 3 days.
> 
> Please review the following webrev
> 
> http://cr.openjdk.java.net/~enevill/8199138/webrev.02
> 
> This has the following additional changes over the previous webrev
> 
> 1) Add comment in os_linux.cpp
> 
> @@ -1733,6 +1733,9 @@
>  #ifndef EM_AARCH64
>    #define EM_AARCH64    183               /* ARM AARCH64 */
>  #endif
> +#ifndef EM_RISCV                          /* RISCV */
> +  #define EM_RISCV      243
> +#endif

What confuses me: Why RISCV here and not RISCV64?

In particular this hunk:

@@ -1758,6 +1761,7 @@
     {EM_PARISC,      EM_PARISC,  ELFCLASS32, ELFDATA2MSB, (char*)"PARISC"},
     {EM_68K,         EM_68K,     ELFCLASS32, ELFDATA2MSB, (char*)"M68k"},
     {EM_AARCH64,     EM_AARCH64, ELFCLASS64, ELFDATA2LSB, (char*)"AARCH64"},
+    {EM_RISCV,       EM_RISCV,   ELFCLASS64, ELFDATA2LSB, (char*)"RISCV"},
   };

I know there is already 32-bit RISC-V and there are actually plans for
using it. So, it looks to me you would be breaking 32-bit RISC-V here.

Adrian

-- 
 .''`.  John Paul Adrian Glaubitz
: :' :  Debian Developer - glaubitz at debian.org
`. `'   Freie Universitaet Berlin - glaubitz at physik.fu-berlin.de
  `-    GPG: 62FF 8A75 84E0 2956 9546  0006 7426 3B37 F5B5 F913