RFC (S) JDK-8050149: Experimental option to select the instruction sequence for x86 StoreLoad barrier

Vitaly Davidovich vitalyd at gmail.com
Mon Jul 14 22:00:10 UTC 2014


In case you're interested (and haven't checked yourself), both clang(3.4.1)
and gcc(4.9) use mfence (under O2+) for
std::atomic_thread_fence(std::memory_order_seq_cst), which I think is
comparable to StoreLoad that's emitted on x86 backend in hotspot.


On Mon, Jul 14, 2014 at 5:53 PM, Aleksey Shipilev <
aleksey.shipilev at oracle.com> wrote:

> Sure, no problems with (non-)inclusion.
>
> My question still stands: are there other things I should try to
> implement as StoreLoad barrier alternative?
>
> Thanks,
> -Aleksey.
>
> On 07/15/2014 01:39 AM, Vladimir Kozlov wrote:
> > Sorry Aleksey, I don't think this code should be in our sources.
> > The patch is small enough to keep it separately when you need it. And
> > the problem is not as big as your previous experimental codes.
> >
> > Thanks,
> > Vladimir
> >
> > On 7/14/14 1:01 PM, Aleksey Shipilev wrote:
> >> Had an off-list discussion with Dave Dice, and figured to throw in a few
> >> other options. Let me know if you think something else is missing from
> >> this list to try:
> >>    http://cr.openjdk.java.net/~shade/8050149/webrev.02/
> >>
> >> -Aleksey.
> >>
> >> On 07/14/2014 07:42 PM, Aleksey Shipilev wrote:
> >>> Hi guys,
> >>>
> >>> Any comments about pushing something like this into HS?
> >>>   https://bugs.openjdk.java.net/browse/JDK-8050149
> >>>   http://cr.openjdk.java.net/~shade/8050149/webrev.01/
> >>>
> >>> This is a follow up for:
> >>>   https://bugs.openjdk.java.net/browse/JDK-8050147
> >>>
> >>> I think the actual switch, if any, should happen in JDK-8050147, but I
> >>> would like to explore the alternatives here. Performance runs are
> >>> underway. Are there any other alternatives for StoreLoad missing?
> >>>
> >>> Thanks,
> >>> -Aleksey.
> >>>
> >>
>
>
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