[jmm-dev] Jmm revision status
dl at cs.oswego.edu
Fri Jul 18 23:15:24 UTC 2014
On 07/18/2014 06:20 PM, Hans Boehm wrote:
> I'm not quite sure what you mean by "the usual benign weirdness"?
I meant (in a thinking-out-loud way): Suppose compilers for ARM
followed your sec 6 rules, but omitted any fence/fence-like
instructions (as in your sec 6.1). Would this lead to different
but solvable problems? But I now see that it does not.
> Preserving load->store ordering (or equivalently requiring rf U hb to be
> acyclic) leads to an observably different memory model from what we have now.
(You might recall that this was the heart of the "causally
consistent, cache coherent" model some of us once explored,
but gave up on mainly because mapping to Power/ARM was a
mystery. Due to Peter et al's work, it is no longer a mystery,
but instead a known practical impossibility.)
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