[jmm-dev] jdk9 APIs
stephan.diestelhorst at arm.com
Tue Aug 25 09:53:56 UTC 2015
On Monday 24 August 2015 09:42:00 Aleksey Shipilev wrote:
> On 08/21/2015 08:54 PM, Doug Lea wrote:
> > On 08/21/2015 09:54 AM, Aleksey Shipilev wrote:
> >>> T compareAndExchangeVolatile(Object owner, T expected, T val);
> >>> T compareAndExchangeAcquire(Object owner, T expected, T val);
> >>> T compareAndExchangeRelease(Object owner, T expected, T val);
> >> Um, I have a stupid question. What's the story with non-x86 processors
> >> here? Do we have any machines that do not have an explicit CAS, but only
> >> have LL/SC? Returning the failure witness does not seem doable with
> >> LL/SC-emulated CAS.
> > With LL/SC, you loop until either compare-failure with the LL'ed value
> > or success of the SC. So either way there is a unique answer.
> Oh, right. I was under (false) impression that you do LL/SC without
> looping, but I guess that is not really viable for strong CAS emulation
> since SC may "spuriously" fail.
Note that, despite the loop, we guarantee lock-freedom:
"In the event of repeatedly-contending Load-Exclusive/Store-Exclusive
instruction sequences from multiple PEs, an implementation must ensure
that forward progress is made by at least one PE." ARM ARM v8
ARM Research - Systems
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