[jmm-dev] bitwise RMW operators, specifically testAndSetBit/BTS
aph at redhat.com
Fri Jul 15 08:06:45 UTC 2016
On 15/07/16 04:16, David Holmes wrote:
> On 15/07/2016 12:09 PM, John Rose wrote:
>> > I think we are missing an important opportunity by not supporting
>> > single-bit RMW operations in VarHandles.
>> > In particular, the x86 "bts" (bit-test-and-test) "btr"
>> > (bit-test-and-reset) and "btc" (bit-test-and-clear) are sometimes
>> > the right way to modify some data structure, when the alternative
>> > is a load and "cmpxchg" in a loop. The overall costs are
>> > probably the same in the best case, but the loop-based idiom has
>> > some danger (relative to the single-instruction idiom) of costs
>> > stemming from larger code size.
> Is this readily supported on non-x86?
On ARMv8, yes.
>> > In a nutshell, testAndSetBitAcquire behaves as if it were built
>> > on top of compareAndExchangeAcquire (which it may on some
>> > platforms).
>> > The outgoing value parameter is not a value but a bit position
>> > within the memory value (zero = LSB, range-checked). On x86 it
>> > compiles to "lock;bts" with appropriate fencing. It is a great
>> > candidate for building a mutex-enter operation.
It's a huge mistake to insist that only a single bit can be set or
cleared. If it just so happens that a "bts" can be used, fine, but to
bake such a restriction into the library and VM is wrong. The C++
atomic functions which do this job are
All of these take a std::memory_order argument. C++ compatibility
should be our starting point for such things, IMO.
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