[jmm-dev] bitwise RMW operators, specifically testAndSetBit/BTS

Doug Lea dl at cs.oswego.edu
Fri Jul 15 16:27:03 UTC 2016

I agree with Andrew. I now think the three C++ bitwise atomic methods were
prematurely triaged out. (Sorry for being the triager.)

On 07/15/2016 04:06 AM, Andrew Haley wrote:

> The C++ atomic functions which do this job are ++, -- +=, -=

These exist both pre- and post- style in both Java and C++,
(getAndIncrement vs incrementAndGet etc), but for bitwise operations ...

> &=, |=, ^=

... only the getAndX forms seem useful, with only Volatile
and Release orderings. Using the default-volatile RMW convention,
this would require 6 methods:

  getAndOrBits, getAndOrBitsRelease,
  getAndAndBits, getAndAndBitsRelease,
  getAndXorBits, getAndXorBitsRelease

(the embedded "AndAnd" is a little jarring but probably inevitable.)

On X86, it would require some compiler work to transform these
into locked-bts etc instructions when applicable, but until they
are, the unoptimized forms would be no worse than hand-build CAS loops.

On ARMv8.1, these translate into new atomic instructions (at least
the "release" forms). Similarly for the upcoming RISC-V specs.


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