[jmm-dev] bitwise RMW operators, specifically testAndSetBit/BTS

Hans Boehm boehm at acm.org
Wed Jul 20 18:42:30 UTC 2016

On Wed, Jul 20, 2016 at 1:25 AM, Paul Sandoz <Paul.Sandoz at oracle.com> wrote:
> > On 20 Jul 2016, at 02:25, Martin Buchholz <martinrb at google.com <mailto:
martinrb at google.com>> wrote:
> > C++ relaxed atomics are (perhaps!) stronger than "plain" in two senses:
truly atomic (!) and single-memory-location-sequentially-consistent.
> Yes, it’s the latter that seems harder to apply.
I'm not sure whether it's "harder to apply" or "less consciously assumed",
i.e. generally implicitly assumed, but without the programmer's awareness.
At least in my experience, memory_order_relaxed tends to be surprisingly
commonly used for what one might call "single word data structures": An
individual word that describes some aspect of the state independent of
other data structures.  I suspect a lot of such code is not prepared to see
such data flip-flop back and forth repeatedly as the result of a single
update.  If a counter is only ever incremented by a single thread,
programmers don't expect it to decrease.  At a minimum, it's much easier to
reason about such code if you don't have to consider this possibility.

All hardware vendors either provide the property by default (errata aside),
or provide a relatively cheap mechanism that adds it (only Itanium that I
know of).

I believe the property is worth its (compiler only on the most commonly
used hardware) performance cost where you have some reason to believe that
the data is concurrently accessed. It's pretty clearly undesirable for
plain non-racing accesses, since it does interfere with compiler
optimization.  I would put it in a similar category to long/double/struct

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