December 2021 Archives by author

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Starting: Wed Dec 1 01:48:01 UTC 2021
Ending: Fri Dec 31 10:07:06 UTC 2021
Messages: 185

CFV: New RISC-V Port Committer: Yadong Wang Yangfei (Felix)
CFV: New RISC-V Port Committer: Yadong Wang Yangfei (Felix)
Test mail service for this list Yangfei (Felix)
CFV: New RISC-V Port Committer: Yanhong Zhu Yangfei (Felix)
CFV: New RISC-V Port Committer: Yanhong Zhu Yangfei (Felix)
Result: New RISC-V Port Committer: Yadong Wang Yangfei (Felix)
[riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr around calls Feilong Jiang
[riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr around calls [v2] Feilong Jiang
[riscv-port] RFR: 8278474: riscv: Enable two more jtreg hotspot tests Feilong Jiang
[riscv-port] Integrated: 8278474: riscv: Enable two more jtreg hotspot tests Feilong Jiang
[riscv-port] RFR: 8278531: riscv: Remove duplicate code bitset_to_fregs Feilong Jiang
[riscv-port] Integrated: 8278531: riscv: Remove duplicate code bitset_to_fregs Feilong Jiang
[riscv-port] RFR: 8278832: riscv: Inconsistency of Java frame offset definition in jdk.hotspot.agent Feilong Jiang
[riscv-port] Integrated: 8278832: riscv: Inconsistency of Java frame offset definition in jdk.hotspot.agent Feilong Jiang
[riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register saving logic in register savers [v2] Feilong Jiang
[riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register saving logic in register savers [v2] Feilong Jiang
[riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register saving logic in register savers [v3] Feilong Jiang
[riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register saving logic in register savers [v3] Feilong Jiang
[riscv-port] RFR: 8278644: riscv: Intrinsify mulAdd Feilong Jiang
[riscv-port] RFR: 8278644: riscv: Intrinsify mulAdd Feilong Jiang
[riscv-port] RFR: 8278644: riscv: Intrinsify mulAdd [v2] Feilong Jiang
[riscv-port] RFR: 8278644: riscv: Intrinsify mulAdd [v2] Feilong Jiang
[riscv-port] Integrated: 8278644: riscv: Intrinsify mulAdd Feilong Jiang
[riscv-port] RFR: 8279213: riscv: RVB: Add zero/sign extend instructions [v2] Feilong Jiang
[riscv-port] RFR: 8279292: riscv: Intrinsify multiplyToLen and squareToLen Feilong Jiang
[riscv-port] RFR: 8279292: riscv: Intrinsify multiplyToLen and squareToLen [v2] Feilong Jiang
[riscv-port] RFR: 8279292: riscv: Intrinsify multiplyToLen and squareToLen [v2] Feilong Jiang
[riscv-port] RFR: 8279292: riscv: Intrinsify multiplyToLen and squareToLen [v2] Feilong Jiang
[riscv-port] RFR: 8279292: riscv: Intrinsify multiplyToLen and squareToLen [v3] Feilong Jiang
[riscv-port] RFR: 8279292: riscv: Intrinsify multiplyToLen and squareToLen [v4] Feilong Jiang
[riscv-port] RFR: 8279292: riscv: Intrinsify multiplyToLen and squareToLen [v5] Feilong Jiang
[riscv-port] RFR: 8279292: riscv: Intrinsify multiplyToLen and squareToLen [v6] Feilong Jiang
[riscv-port] Integrated: 8279292: riscv: Intrinsify multiplyToLen and squareToLen Feilong Jiang
[riscv-port] RFR: 8279344: riscv: RVB: Add bitwise rotation instructions Feilong Jiang
[riscv-port] RFR: 8279344: riscv: RVB: Add bitwise rotation instructions [v2] Feilong Jiang
[riscv-port] RFR: 8279344: riscv: RVB: Add bitwise rotation instructions [v3] Feilong Jiang
[riscv-port] RFR: 8279344: riscv: RVB: Add bitwise rotation instructions [v4] Feilong Jiang
[riscv-port] RFR: 8279344: riscv: RVB: Add bitwise rotation instructions [v5] Feilong Jiang
CFV: New RISC-V Port Committer: Yadong Wang Edward Nevill
[riscv-port] RFR: 8278033: riscv: Fix MacroAssembler::atomic_incw: store condition instruction has wrong operand order Aleksey Shipilev
[riscv-port] RFR: 8278033: riscv: Fix MacroAssembler::atomic_incw: store condition instruction has wrong operand order Aleksey Shipilev
[riscv-port] RFR: 8276832: riscv: typo in LIR_Assembler::check_no_conflict Aleksey Shipilev
CFV: New RISC-V Port Committer: Yadong Wang Aleksey Shipilev
CFV: New RISC-V Port Committer: Yanhong Zhu Aleksey Shipilev
[riscv-port] RFR: 8278041: riscv: Use t2 as the dedicated machine flags register in C2 Yadong Wang
[riscv-port] RFR: 8278041: riscv: Use t2 as the dedicated machine flags register in C2 [v2] Yadong Wang
[riscv-port] RFR: 8278041: riscv: Use t2 as the dedicated machine flags register in C2 [v2] Yadong Wang
[riscv-port] RFR: 8278041: riscv: Use t2 as the dedicated machine flags register in C2 [v2] Yadong Wang
[riscv-port] RFR: 8278192: riscv: remove unnecessary instruct of DecodeNKlass in C2 Yadong Wang
[riscv-port] RFR: 8278192: riscv: remove unnecessary instruct of DecodeNKlass in C2 Yadong Wang
[riscv-port] RFR: 8278192: riscv: remove unnecessary instruct of DecodeNKlass in C2 [v2] Yadong Wang
[riscv-port] Integrated: 8278192: riscv: remove unnecessary instruct of DecodeNKlass in C2 Yadong Wang
[riscv-port] RFR: 8278322: riscv: Support RVC: compressed instructions Yadong Wang
[riscv-port] RFR: 8278322: riscv: Support RVC: compressed instructions Yadong Wang
[riscv-port] RFR: 8278387: riscv: Implement UseHeavyMonitors consistently Yadong Wang
[riscv-port] Integrated: 8278387: riscv: Implement UseHeavyMonitors consistently Yadong Wang
[riscv-port] RFR: 8278322: riscv: Support RVC: compressed instructions Yadong Wang
[riscv-port] RFR: 8278743: riscv: Remove the x4 register saving logic in Java frames Yadong Wang
[riscv-port] RFR: 8278041: riscv: Use t2 as the dedicated machine flags register in C2 [v2] Yadong Wang
[riscv-port] Withdrawn: 8278041: riscv: Use t2 as the dedicated machine flags register in C2 Yadong Wang
[riscv-port] RFR: 8278832: riscv: Inconsistency of Java frame offset definition in jdk.hotspot.agent Yadong Wang
[riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register saving logic in register savers Yadong Wang
[riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register saving logic in register savers [v2] Yadong Wang
[riscv-port] RFR: 8278547: riscv: Refactor moving assembler functions for vector instructions into separate file Yadong Wang
[riscv-port] RFR: 8278895: riscv: Rename Riscv64 to RISCV64 [v2] Yadong Wang
[riscv-port] RFR: 8278890: riscv: Missing features string in VM_Version Yadong Wang
[riscv-port] Integrated: 8278890: riscv: Missing features string in VM_Version Yadong Wang
[riscv-port] RFR: 8278033: riscv: Fix MacroAssembler::atomic_incw: store condition instruction has wrong operand order Fei Yang
[riscv-port] RFR: 8278034: riscv: Fix callee-saved float register definitions: should be SOE Fei Yang
[riscv-port] RFR: 8278041: riscv: Use t2 as the dedicated machine flags register in C2 Fei Yang
[riscv-port] RFR: 8278041: riscv: Use t2 as the dedicated machine flags register in C2 Fei Yang
[riscv-port] RFR: 8278041: riscv: Use t2 as the dedicated machine flags register in C2 [v2] Fei Yang
[riscv-port] RFR: 8278192: riscv: remove unnecessary instruct of DecodeNKlass in C2 Fei Yang
[riscv-port] RFR: 8278192: riscv: remove unnecessary instruct of DecodeNKlass in C2 [v2] Fei Yang
[riscv-port] RFR: 8278192: riscv: remove unnecessary instruct of DecodeNKlass in C2 [v2] Fei Yang
[riscv-port] RFR: 8278322: riscv: Support RVC: compressed instructions Fei Yang
[riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr around calls [v2] Fei Yang
[riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr around calls [v2] Fei Yang
[riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr around calls [v2] Fei Yang
[riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr around calls [v2] Fei Yang
[riscv-port] RFR: 8278387: riscv: Implement UseHeavyMonitors consistently Fei Yang
[riscv-port] RFR: 8278322: riscv: Support RVC: compressed instructions Fei Yang
[riscv-port] RFR: 8278322: riscv: Support RVC: compressed instructions Fei Yang
[riscv-port] RFR: 8278322: riscv: Support RVC: compressed instructions Fei Yang
[riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr around calls [v3] Fei Yang
[riscv-port] RFR: 8278474: riscv: Enable two more jtreg hotspot tests Fei Yang
[riscv-port] RFR: 8278322: riscv: Support RVC: compressed instructions Fei Yang
[riscv-port] RFR: 8278531: riscv: Remove duplicate code bitset_to_fregs Fei Yang
[riscv-port] RFR: 8278041: riscv: Use t2 as the dedicated machine flags register in C2 [v2] Fei Yang
[riscv-port] RFR: 8278743: riscv: Remove the x4 register saving logic in Java frames Fei Yang
[riscv-port] RFR: 8278832: riscv: Inconsistency of Java frame offset definition in jdk.hotspot.agent Fei Yang
[riscv-port] RFR: 8278547: riscv: Refactor moving assembler functions for vector instructions into separate file Fei Yang
git: openjdk/riscv-port: riscv-port: 8278547: riscv: Refactor moving assembler functions for vector instructions into separate file Fei Yang
[riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register saving logic in register savers [v3] Fei Yang
[riscv-port] RFR: 8278895: riscv: Rename Riscv64 to RISCV64 [v3] Fei Yang
[riscv-port] RFR: 8278890: riscv: Missing features string in VM_Version Fei Yang
[riscv-port] RFR: 8278644: riscv: Intrinsify mulAdd Fei Yang
[riscv-port] RFR: 8278994: riscv: RVC: basic instruction set Fei Yang
[riscv-port] RFR: 8278644: riscv: Intrinsify mulAdd Fei Yang
[riscv-port] RFR: 8278644: riscv: Intrinsify mulAdd [v2] Fei Yang
[riscv-port] RFR: 8278644: riscv: Intrinsify mulAdd [v2] Fei Yang
[riscv-port] RFR: 8278994: riscv: RVC: basic instruction set Fei Yang
[riscv-port] RFR: 8279292: riscv: Intrinsify multiplyToLen and squareToLen Fei Yang
[riscv-port] RFR: 8279292: riscv: Intrinsify multiplyToLen and squareToLen [v4] Fei Yang
[riscv-port] RFR: 8279292: riscv: Intrinsify multiplyToLen and squareToLen [v6] Fei Yang
git: openjdk/riscv-port: riscv-port: 8279292: riscv: Intrinsify multiplyToLen and squareToLen Fei Yang
[riscv-port] RFR: 8278033: riscv: Fix MacroAssembler::atomic_incw: store condition instruction has wrong operand order Xiaolin Zheng
[riscv-port] RFR: 8278034: riscv: Fix callee-saved float register definitions: should be SOE Xiaolin Zheng
[riscv-port] Integrated: 8278033: riscv: Fix MacroAssembler::atomic_incw: store condition instruction has wrong operand order Xiaolin Zheng
[riscv-port] RFR: 8278034: riscv: Fix callee-saved float register definitions: should be SOE Xiaolin Zheng
[riscv-port] Integrated: 8278034: riscv: Fix callee-saved float register definitions: should be SOE Xiaolin Zheng
[riscv-port] RFR: 8277890: riscv: fix the infinite LR/SC loop in BarrierSetAssembler::eden_allocate Xiaolin Zheng
[riscv-port] RFR: 8278033: riscv: Fix MacroAssembler::atomic_incw: store condition instruction has wrong operand order Xiaolin Zheng
[riscv-port] RFR: 8278322: riscv: Support RVC: compressed instructions Xiaolin Zheng
[riscv-port] RFR: 8278322: riscv: Support RVC: compressed instructions Xiaolin Zheng
[riscv-port] RFR: 8278322: riscv: Support RVC: compressed instructions Xiaolin Zheng
[riscv-port] RFR: 8278322: riscv: Support RVC: compressed instructions Xiaolin Zheng
[riscv-port] RFR: 8278322: riscv: Support RVC: compressed instructions Xiaolin Zheng
[riscv-port] RFR: 8278322: riscv: Support RVC: compressed instructions Xiaolin Zheng
[riscv-port] RFR: 8278322: riscv: Support RVC: compressed instructions Xiaolin Zheng
[riscv-port] Withdrawn: 8278322: riscv: Support RVC: compressed instructions Xiaolin Zheng
[riscv-port] RFR: 8278322: riscv: Support RVC: compressed instructions Xiaolin Zheng
[riscv-port] RFR: 8278743: riscv: Remove the x4 register saving logic in Java frames Xiaolin Zheng
[riscv-port] RFR: 8278743: riscv: Remove the x4 register saving logic in Java frames Xiaolin Zheng
[riscv-port] Integrated: 8278743: riscv: Remove the x4 register saving logic in Java frames Xiaolin Zheng
[riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register saving logic in register savers Xiaolin Zheng
[riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register saving logic in register savers [v2] Xiaolin Zheng
[riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register saving logic in register savers [v2] Xiaolin Zheng
[riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register saving logic in register savers [v2] Xiaolin Zheng
[riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register saving logic in register savers [v2] Xiaolin Zheng
[riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register saving logic in register savers [v2] Xiaolin Zheng
[riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register saving logic in register savers [v3] Xiaolin Zheng
[riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register saving logic in register savers [v2] Xiaolin Zheng
[riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register saving logic in register savers [v3] Xiaolin Zheng
[riscv-port] Integrated: 8278833: riscv: Remove the x3 and x4 register saving logic in register savers Xiaolin Zheng
[riscv-port] RFR: 8278994: riscv: RVC: basic instruction set Xiaolin Zheng
[riscv-port] RFR: 8278994: riscv: RVC: basic instruction set Xiaolin Zheng
[riscv-port] RFR: 8278994: riscv: RVC: basic instruction set Xiaolin Zheng
[riscv-port] RFR: 8278994: riscv: RVC support [v2] Xiaolin Zheng
[riscv-port] RFR: 8278994: riscv: RVC support [v2] Xiaolin Zheng
[riscv-port] RFR: 8278994: riscv: RVC support [v2] Xiaolin Zheng
[riscv-port] RFR: 8278994: riscv: RVC support [v2] Xiaolin Zheng
[riscv-port] RFR: 8278994: riscv: RVC support [v2] Xiaolin Zheng
[riscv-port] RFR: 8278994: riscv: RVC support [v3] Xiaolin Zheng
[riscv-port] RFR: 8278994: riscv: RVC support [v2] Xiaolin Zheng
[riscv-port] RFR: 8276832: riscv: typo in LIR_Assembler::check_no_conflict Yanhong Zhu
[riscv-port] RFR: 8276832: riscv: typo in LIR_Assembler::check_no_conflict Yanhong Zhu
[riscv-port] Integrated: 8276832: riscv: typo in LIR_Assembler::check_no_conflict Yanhong Zhu
[riscv-port] RFR: 8278832: riscv: Inconsistency of Java frame offset definition in jdk.hotspot.agent Yanhong Zhu
[riscv-port] RFR: 8278547: riscv: Refactor moving assembler functions for vector instructions into separate file Yanhong Zhu
[riscv-port] Integrated: 8278547: riscv: Refactor moving assembler functions for vector instructions into separate file Yanhong Zhu
[riscv-port] RFR: 8278895: riscv: Rename Riscv64 to RISCV64 Yanhong Zhu
[riscv-port] RFR: 8278895: riscv: Rename Riscv64 to RISCV64 [v2] Yanhong Zhu
[riscv-port] RFR: 8278895: riscv: Rename Riscv64 to RISCV64 [v3] Yanhong Zhu
[riscv-port] RFR: 8278895: riscv: Rename Riscv64 to RISCV64 [v2] Yanhong Zhu
[riscv-port] Integrated: 8278895: riscv: Rename Riscv64 to RISCV64 Yanhong Zhu
[riscv-port] RFR: 8279346: riscv: Unnecessary sign extension in BigInteger intrinsics Yanhong Zhu
git: openjdk/riscv-port: riscv-port: 94 new changesets duke
git: openjdk/riscv-port: riscv-port: 55 new changesets duke
git: openjdk/riscv-port: riscv-port: 46 new changesets duke
git: openjdk/riscv-port: riscv-port: 65 new changesets duke
git: openjdk/riscv-port: riscv-port: 31 new changesets duke
git: openjdk/riscv-port: riscv-port: 39 new changesets duke
git: openjdk/riscv-port: riscv-port: 31 new changesets duke
git: openjdk/riscv-port: riscv-port: 2 new changesets duke
git: openjdk/riscv-port: riscv-port: 6 new changesets duke
[riscv-port] RFR: 8278895: riscv: Rename Riscv64 to RISCV64 [v2] guotaiping1
[riscv-port] RFR: 8278895: riscv: Rename Riscv64 to RISCV64 [v3] guotaiping1
[riscv-port] RFR: 8278644: riscv: Intrinsify mulAdd [v2] guotaiping1
[riscv-port] RFR: 8279292: riscv: Intrinsify multiplyToLen and squareToLen [v4] guotaiping1
[riscv-port] RFR: 8277968: riscv: Detect vector extension with vcsr [v2] kuaiwei
[riscv-port] RFR: 8278041: riscv: Use t2 as the dedicated machine flags register in C2 [v2] kuaiwei
[riscv-port] RFR: 8277968: riscv: Detect vector extension with vcsr [v2] kuaiwei
[riscv-port] Withdrawn: 8277968: riscv: Detect vector extension with vcsr kuaiwei
[riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr around calls kuaiwei
[riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr around calls kuaiwei
[riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr around calls [v2] kuaiwei
[riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr around calls [v2] kuaiwei
[riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr around calls [v3] kuaiwei
[riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr around calls [v2] kuaiwei
[riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr around calls [v2] kuaiwei
[riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr around calls [v3] kuaiwei
[riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr around calls [v3] kuaiwei
[riscv-port] Integrated: 8278337: riscv: remove unnecessary ld/sd zr around calls kuaiwei
[riscv-port] RFR: 8278041: riscv: Use t2 as the dedicated machine flags register in C2 [v2] kuaiwei

Last message date: Fri Dec 31 10:07:06 UTC 2021
Archived on: Fri Dec 31 10:07:15 UTC 2021

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