[riscv-port] RFR: 8278994: riscv: RVC support [v10]

[Xiaolin Zheng]

On Sat, 8 Jan 2022 11:11:21 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Xiaolin Zheng has updated the pull request with a new target base due to a merge or a rebase. The pull request now contains 14 commits:
>> 
>>  - Move RVC code to the proper location after rebasing (#42)
>>  - Rename misc functions and change the positions of some comments
>>  - Remove remaining macros as discussions
>>  - Remain an 'minimum_alignment' unchanged
>>  - Manually inline all macros into functions as discussions
>>  - Remove assembler_riscv_c.hpp as discussions
>>  - Remove COMPRESSIBLE & NOT_COMPRESSIBLE macros by adding one layer as discussions
>>  - Fix remaining CEXT -> RVC
>>  - Remove Alignment-related changes as discussions
>>  - Update licenses to the new year
>>  - ... and 4 more: https://git.openjdk.java.net/riscv-port/compare/c7944edf...2a6ff151
>
> src/hotspot/cpu/riscv/assembler_riscv.hpp line 2409:
> 
>> 2407:   }
>> 2408: 
>> 2409: #define IF(BOOL, ...)       IF_##BOOL(__VA_ARGS__)
> 
> maybe better to expand those macros directly?

Unfortunately, this could not be easily done by substituting by a simple `assert_cond(!CHECK_RD || Rd != x0);` because of some details:
`c_ldsp` and `c_fldsp` use `Register` and `FloatRegister` separately so there is a type-related problem: x0 is only one `Register` and only `c_ldsp` needs this sanity check. So these macros here are trying to make sure this check isn't generated by `c_fldsp` at all because checking `Rd(a float register) != x0` will result in compilation errors.

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PR: https://git.openjdk.java.net/riscv-port/pull/34