[aarch64-port-dev ] Simplify memory barrier generation

[Andrew Haley]

This patch doesn't make memory barriers any different, it just makes them
easier to read and write.  Now, you can just say something like

    membar(Assembler::StoreStore|Assembler::StoreLoad);

Andrew.


# HG changeset patch
# User aph
# Date 1380807225 -3600
# Node ID 1b73f7fb6f30402ed55ac131125d5d9d28a9c710
# Parent  2a22f57aad360e0e2d615da94e0bff2a98fe9ea2
Simplify memory barrier generation

diff -r 2a22f57aad36 -r 1b73f7fb6f30 src/cpu/aarch64/vm/assembler_aarch64.hpp
--- a/src/cpu/aarch64/vm/assembler_aarch64.hpp	Fri Oct 04 13:16:35 2013 +0100
+++ b/src/cpu/aarch64/vm/assembler_aarch64.hpp	Thu Oct 03 14:33:45 2013 +0100
@@ -995,6 +995,19 @@
     system(0b01, 0b011, 0b0111, 0b0101, 0b001, Rt);
   }

+  // A more convenient access to dmb for our purposes
+  enum Membar_mask_bits {
+    StoreStore = ST,
+    LoadStore  = LD,
+    LoadLoad   = LD,
+    StoreLoad  = SY,
+    AnyAny     = SY
+  };
+
+  void membar(Membar_mask_bits order_constraint) {
+    dmb(Assembler::barrier(order_constraint));
+  }
+
   // Unconditional branch (register)
   void branch_reg(Register R, int opc) {
     starti;
diff -r 2a22f57aad36 -r 1b73f7fb6f30 src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp	Fri Oct 04 13:16:35 2013 +0100
+++ b/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp	Thu Oct 03 14:33:45 2013 +0100
@@ -2883,10 +2883,10 @@

 void LIR_Assembler::membar() {
   COMMENT("membar");
-  __ dsb(__ SY);
+  __ membar(MacroAssembler::AnyAny);
 }

-void LIR_Assembler::membar_acquire() {
+void LIR_Assembler::membar_acquire() {
   __ block_comment("membar_acquire");
 }

@@ -2898,7 +2898,7 @@

 void LIR_Assembler::membar_storestore() {
   COMMENT("membar_storestore");
-  __ dsb(__ ST);
+  __ membar(MacroAssembler::StoreStore);
 }

 void LIR_Assembler::membar_loadstore() { Unimplemented(); }
diff -r 2a22f57aad36 -r 1b73f7fb6f30 src/cpu/aarch64/vm/macroAssembler_aarch64.hpp
--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp	Fri Oct 04 13:16:35 2013 +0100
+++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp	Thu Oct 03 14:33:45 2013 +0100
@@ -1331,30 +1331,6 @@
     Label*   retaddr = NULL
   );

-  enum Membar_mask_bits {
-    StoreStore = 1 << 3,
-    LoadStore  = 1 << 2,
-    StoreLoad  = 1 << 1,
-    LoadLoad   = 1 << 0
-  };
-
-  void membar(Membar_mask_bits order_constraint) {
-    // LD     Load-Load, Load-Store
-    // ST     Store-Store
-    // SY     Any-Any
-
-    // Handle simple cases first
-    if (order_constraint == StoreStore) {
-      dsb(ST);
-    } else if (order_constraint == LoadLoad
-	|| order_constraint == LoadStore
-	|| order_constraint == (LoadLoad | LoadStore)) {
-      dsb(LD);
-    } else {
-      dsb(SY);
-    }
-  }
-
   void ldr_constant(Register dest, address const_addr) {
     guarantee(const_addr, "constant pool overflow");
     if (NearCpool) {