[aarch64-port-dev ] cmpxchg and memory barriers

[D.Sturm]

Thanks for the clarification.
I'll keep an eye out for all changes in that area.. I can reuse a good deal
of it and it's reassuring to say the least if I can just copy code that
people who understand all the intricacies of the memory model have blessed.

--Daniel


On 21 March 2014 17:58, Andrew Haley <aph at redhat.com> wrote:

> On 03/21/2014 03:17 PM, D.Sturm wrote:
>
> > I'm wondering, why is the first instruction in the loop of
> > MacroAssembler::cmpxchg functions an AnyAny memory barrier?
> >
> > As I understand it, an ldxr instruction gives all the memory guarantees
> of
> > a volatile read, and "stxr; AnyAny" gives the same guarantees as a
> volatile
> > write. The CAS instruction has the same guarantees as both a volatile
> read
> > and write.
> >
> > Am I misunderstanding the Aarch64 memory model (or the JMM - I go mostly
> by
> > http://g.oswego.edu/dl/jmm/cookbook.html) or is the first barrier really
> > superfluous?
>
> You're probably right: we know at the moment that we are emitting far too
> many barriers.  This has been the subject of a great deal of discussion and
> meetings with concurrency gurus.  I will fix it as part of a cleanup in
> this area.
>
> Andrew.
>
>