[aarch64-port-dev ] cmpxchg and memory barriers

Andrew Haley aph at redhat.com
Fri Mar 21 17:34:36 UTC 2014


On 03/21/2014 05:28 PM, D.Sturm wrote:
> Thanks for the clarification.
> I'll keep an eye out for all changes in that area.. I can reuse a good deal
> of it and it's reassuring to say the least if I can just copy code that
> people who understand all the intricacies of the memory model have blessed.

I'm not sure that any such person exists.  Quoth Hans Boehm:

    As far as I know, the ARMv8 acquire/release operations were
    designed specifically to act as Java volatile or C++
    memory_order_seq_cst load/store operations, without the kind of
    ordering overkill that we currently need on x86, i.e. they were
    designed to get us to the "better world".

    My main remaining concern is that we don't have a complete, much
    less provably correct, mapping of either Java or C++ atomics to
    this ISA...

Andrew.



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