[aarch64-port-dev ] cmpxchg and memory barriers

[D.Sturm]

Interesting tidbit - shouldn't have been surprised then how nicely acq/rel
semantics fit the JMM, but makes sense.

Hopefully we'll have some more progress in that area, it's definitely the
area in the whole compiler I'm the most at unease about and it's by far the
hardest to test (FP behavior is interesting too but we have good tests for
it and it's deterministic).

-- Daniel


On 21 March 2014 18:34, Andrew Haley <aph at redhat.com> wrote:

> On 03/21/2014 05:28 PM, D.Sturm wrote:
> > Thanks for the clarification.
> > I'll keep an eye out for all changes in that area.. I can reuse a good
> deal
> > of it and it's reassuring to say the least if I can just copy code that
> > people who understand all the intricacies of the memory model have
> blessed.
>
> I'm not sure that any such person exists.  Quoth Hans Boehm:
>
>     As far as I know, the ARMv8 acquire/release operations were
>     designed specifically to act as Java volatile or C++
>     memory_order_seq_cst load/store operations, without the kind of
>     ordering overkill that we currently need on x86, i.e. they were
>     designed to get us to the "better world".
>
>     My main remaining concern is that we don't have a complete, much
>     less provably correct, mapping of either Java or C++ atomics to
>     this ISA...
>
> Andrew.
>
>